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 1. homeSiemens Digital Industries Software
 2. RISC-V Enhanced Trace Encoder

Fact Sheet


RISC-V ENHANCED TRACE ENCODER

A complete trace solution for RISC-V processors





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The Tessent™ Enhanced Trace Encoder is a fully‑featured RISC‑V trace solution
that provides a mechanism to monitor the program execution of a CPU in real
time. It encodes program execution (instruction trace) and optionally, the data
from load and store instructions (data trace), outputting trace in a highly
compressed format. External software can later take this data and use it to
reconstruct the program execution flow. The Enhanced Trace Encoder can be finely
tuned to balance the features and gate-count requirements of your system and
includes a broad range of filters, giving complete control over what and when to
trace. It complies with the latest standards produced by the RISC‑V
International’s Efficient Trace for RISC‑V (E‑Trace) Working Group, supporting
any standards‑compliant RISC‑V processor.


THE NEED FOR RISC-V TRACE

Complex systems are prone to imperfect software behaviors. These imperfections
may be due to several factors, for example, interactions with other processor
cores or peripherals, tight timing budgets, poor implementation, or a
combination of the above. The imperfections impact the real‑time behavior of the
system. Software that is not designed to minimize these imperfections leads to
avoidable costs, attributed to underutilized CPUs, heating, power consumption,
post-deployment defects, crashes, and poor longevity of the systems.

Understanding software behavior can be challenging but is key to tackling the
imperfections. Therefore, providing software developers visibility of program
execution is vital. Processor trace capability enables the software engineer to
view the behavior of a program in detail, instruction‑by‑instruction without
disrupting the system.


EFFFICIENT TRACE FOR RISC-V SPECIFICATION

The Efficient Trace for RISC‑V specification specifies a minimum level of trace
functionality. The Enhanced Trace Encoder satisfies the full requirements of the
Efficient Trace specification, while including many additional features not
typically found within implementations provided by CPU vendors or in the
open-source community. The following list of features are few of the many
features offered by the Tessent Enhanced Trace Encoder.

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PRODUCTS

Tessent Embedded Analytics

INDUSTRY SECTOR

Electronics & Semiconductor


RELATED RESOURCES

Solution Brief


RISC-V DEBUG AND TRACE WITH TESSENT EMBEDDED ANALYTICS

Best-in-class RISC-V debug and trace solutions.

White Paper


HIERARCHICAL DFT IN A RISC-V PROCESSOR

This paper demonstrates the application of the Tessent hierarchical DFT and ATPG
methodology on a RISC-V processor. With hierarchical DFT, all the DFT is
completed at the block level and then replicated to the top level.

Verification Academy


RISC-V CORE AND SOC: COMPLIANCE, VERIFICATION, CUSTOMIZATION

In this session you will learn about the balancing act for RISC-V, and go
through flows, tools and models for compliance, verification and adding custom
instructions using various case studies.