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Low Power, High Performance, High Reliability
Home Products Arora V FPGAs
Arora V FPGAs
LittleBee FPGAs
Arora FPGAs
GoBridge ASSP
GOWIN ® EDA
Arora V FPGAs
Contact Sales Request Sample
Features GW5A
(Traditional FPGA) GW5AT
(Transceivers) GW5AR
(Integrated RAM) GW5AS
(ARM Cortex-M3) GW5AST
(RISC-V AE350) GW5ART
(ARM + Transceivers) GW5ANT
(Flash+Transceivers) GW5ANRT
(Flash+RAM+
Transceivers) GW5AT
(Automotive) GW5A
(Automotive) Documentation
Features
Features GW5A
(Traditional FPGA) GW5AT
(Transceivers) GW5AR
(Integrated RAM) GW5AS
(ARM Cortex-M3) GW5AST
(RISC-V AE350) GW5ART
(ARM + Transceivers) GW5ANT
(Flash+Transceivers) GW5ANRT
(Flash+RAM+
Transceivers) GW5AT
(Automotive) GW5A
(Automotive) Documentation
GOWINSEMI’s Arora V FPGA series provides SRAM-based FPGA devices with increased
logic resources, interfaces and performance. Arora V FPGAs include DDR3 memory
interfacing, 12.5Gbps CDR-based SERDES supporting multiple protocols and
flexible packaging options making it the ideal choice for communications,
server, imaging, and automotive applications requiring high interface and
computing throughput by providing best performance/watt.
Arora V is supported by GOWIN EDA providing an efficient and easy-to-use FPGA
hardware development environment support multiple RTL-based programming
languages, synthesis, placement & routing, bitstream generation and download,
power analysis and in-device logic analyzer.
Arora V FPGA Product Features
FPGA Fabric Architecture
* Up to 138K LUTs(GW5A(S)(T)-138)
* Up to 23K LUTs(GW5A-25)
* Block SRAM with multiple modes
* Single Port, Semi-Dual Port, True Dual Port, and Semi Dual Port with ECC
function
* Byte write enable
* ECC error detection and correction
* High performance DSP
* Multipliers support 12x12, 27x36, 27x18-bit modes
* Includes 48-bit accumulator
* Supports DSP cascading
* Embedded pipeline and bypass registers
* Pre-addition operation for filter function
* Internal feedback loop and barrel shifter
* Advanced Clocking
* Up to 16 global clocks
* Up to 6/12 high-performance PLLs
* Up to 16/24 high speed edge clocks
Flexible GPIO
* Adjustable drive strength
* 4mA, 8mA, 12mA, 16mA, 24mA drive
* Bus keeper, pull up/down, and open drain
* Hot Socket and input hysteresis
* Slew Rate option for output signal
ADC
* 60dB SNR and 1kHz Signal Bandwidth
* Flexible X-channel oversampling ADC
* No external voltage source required
Configuration & Programming
* JTAG, SSPI, MSPI, CPU, and SERIAL
* Background programming
* SPI Flash Programming and Boot
* Multi-boot
* Bitstream encryption and Security
* Configuration Memory Soft Error Recovery(CMSER)
* mDRP(GW5A)
* Supports OTP, each device has a unique 64-bit DNA identifier
High Speed Interfaces
* SERDES(GW5AT, GW5AST)
* 270Mbps-12.5Gbps operation
* CDR (Clock Data Recovery)
* Dedicated RX and TX Channels
* Integrated 8b/10b encoder/decoder
* PCIe 2.0 hardcore
* x1, x2, x4, x8 lanes
* Supports root complex and end point
* GW5AST series of FPGA products provide a hardcore processor RiscV AE350_SOC
* MIPI D-PHY RX hardcore(GW5A(S)(T)-138)
* 20Gbps D-PHY RX Hard PHY
* 8 data lanes + 2 clock lanes
* 2.5Gbps/lane
* Built-in SoT HS-Sync, word and lane alignment
* MIPI DSI and MIPI CSI-2 RX link layer IPs
* MIPI D-PHY RX/TX hardcore(GW5A-25)
* 4 data lanes + 1 clock lane
* 2.5Gbps/lane(RX/TX)
* Built-in SoT HS-Sync, word and lane alignment
* MIPI DSI and MIPI CSI-2 RX link layer IPs
* GPIOs supports D-PHY RX/TX(GW5A-25)
* 1.2Gbps/lane
* GPIOs can be configured as MIPI DSI and MIPI CSI-2 RX/TX device interface
* GPIOs support MIPI D-PHY RX(GW5A(S)(T)-138)
* 1.5Gbps/lane
* GPIOs can be configured as MIPI DSI and MIPI CSI-2 RX device interface
* Supports MIPI C-PHY RX/TX Hardcore
* One MIPI Quad supports up to 3 three-wire data lanes
* MIPI C-PHY TX/RX supports up to 2.5 Gsps data rate per lane
* GPIO supports MIPI C-PHY RX/MIPI IO
* External DRAM Interfaces
* Supports various memory types
* DDR2, DDR3, PSRAM, HyperRAM, RPC
* Up to 1333 Mbps (GW5A(S)(T)-138) or 1066 Mbps (GW5A-25)
GW5A Series Table
Device GW5A-25 GW5A-60 GW5A-138 LUT4 23040 59904 138240 REG 23040 59904 138240
Shadow SRAM SSRAM (kb) 180 468 1080 Block SRAM BSRAM (kb) 1008 2124 6120 Number
of BSRAM 56 118 340 DSP 28 118 298 PLLs 6 8 12 Global Clock 16 16 16 HCLK 16 20
24 Transceivers 0 0 0 Transceivers Rate N/A N/A N/A PCle 2.0 0 0 0 LVDS Gbps
1.25 1.25 1.25 DDR3 Mbps 1066 1333 1333 MIPI D-PHY Hardcore
2.5Gbps(RX/TX)
4 Data Lanes
1 Clock Lane
2.5Gbps(RX/TX)
4 Data Lanes
1 Clock Lane
2.5Gbps(RX)
8 Data Lanes
2 Clock Lanes
MIPI C-PHY Hardcore
-
2.5Gsps (RX/TX)
3-trios data lanes
-
ADC 1 2 2 Number of GPIO Banks 8 11 6 Max. GPIOs 239 320 312 Core Voltage Typ.
0.9V/1.0V/1.2V 0.9V/1.0V/1.2V 0.9V/1.0V
--------------------------------------------------------------------------------
Package Options and Availible User I/O (LVDS Pairs):
Package Pitch (mm)
Size(mm)
GW5A-25 GW5A-60 GW5A-138 MIPI D-PHY Harcore MG121N 0.5 6 x 6 82(36) - -
RX/TX Configurable
4 data lanes
1 clock lane
UG324S 0.8 15 x 15 239(116) 226(110) - UG256C 0.8 14 x 14 191(90) - - PG256C
1.0 17 x 17 191(90) - - PG256 1.0 17 x 17 184 (88) - -
RX/TX Configurable
4 data lanes
1 clock lane
PG256S 1.0 17 x 17 194(93) - - UG324 0.8 15 x 15 222(104) - -
RX/TX Configurable
4 data lanes
1 clock lane
UG324A 0.8 15 x 15 - 222(106) 222(106)
UG324F
0.8
15 x 15
223(108)
-
-
RX/TX Configurable
4 data lanes
1 clock lane
MG196S
0.5
8 x 8
114（53）
-
-
PG196S
1.0
15 x 15
110(48)
-
-
RX/TX Configurable
4 data lanes
1 clock lane
UG225S
0.8
13 x 13
168（80）
-
-
LQ100
0.5
14 x 14
80(36)
-
-
LQ144
0.5
20 x 20
109(50)
-
-
Note!
* The number of PLLs supported by different packages is different, here is the
maximum value.
* In addition to the GPIO Bank, it also includes a JTAG Bank with 4 I/Os and a
Config Bank with 1 I/O.
* The EV version has a built-in LDO, and VCC can support 1.2V.
GW5AT Series Table
Device GW5AT-15 GW5AT-60 GW5AT-75 GW5AT-138 LUT4 15120 59,904 86688 138240 REG
15120 59,904 86688 138240 Shadow SRAM SSRAM (kb) 118.125 468 677 1080 Block SRAM
BSRAM (kb) 630 2124 4608 6120 Number of BSRAM 35 118 256 340 DSP 28 118 213 298
PLLs 2 8 12 12 Global Clock 16 16 16 16 HCLK 2 20 24 24 Transceivers 4 4 8 8
Transceivers Rate 270Mbps-
12.5Gbps
270Mbps-
12.5Gbps
270Mbps-
12.5Gbps
270Mbps-
12.5Gbps
PCle
1,
x1, x2, x4 PCIe 3.0
1,
x1, x2, x4 PCIe 2.0
1,
x1, x2, x4, x8 PCIe 2.0
1,
x1, x2, x4, x8 PCIe 2.0
LVDS Gbps 1.25 1.25 1.25 1.25 DDR3 Mbps - 1333 1333 1333 MIPI D-PHY Hardcore
2.5Gbps(RX/TX)
4 Data Lanes
1 Clock Lanes
2.5Gbps(RX/TX)
4 Data Lanes
1 Clock Lanes
2.5Gbps(RX)
8 Data Lanes
2 Clock Lanes
2.5Gbps(RX)
8 Data Lanes
2 Clock Lanes
MIPI C-PHY Hardcore
2.5Gsps
(=5.75Gbps,RX/TX),
3-trios data lanes
2.5Gsps
(=5.75Gbps,RX/TX),
3-trios data lanes
-
-
ADC 1 2 2 2 Number of GPIO Banks 4 11 6 6 Max. GPIOs 53 320 312 312 Core Voltage
Typ. 0.9V 0.9V/1.0V/1.2V 0.9V/1.0V 0.9V/1.0V
--------------------------------------------------------------------------------
GW5AT-138 Package Options and Available User I/O (LVDS Pairs):
Package Type Decription Pitch (mm)
Size
(mm)
GW5AT-138
(True LVDS Pairs) Transceivers MIPI D-PHY Hardcore FPG676A FCPBGA Flip Chip 1.0
27 x 27 311(150) 8
RX
8 data lanes
2 clock lanes
PG484A PBGA Wire Bond 1.0 23 x 23 291(143) 4
-
PG484
PBGA
Wire Bond
1.0
23 x 23
271(133)
4
RX
8 data lanes
2 clock lanes
PG676A
PBGA
Wire Bond
1.0
27 x 27
311(150)
8
RX
8 data lanes
2 clock lanes
UG324A
UBGA
Wire Bond
0.8
15 x 15
141(68)
4
RX
8 data lanes
2 clock lanes
GW5AT-60 Package Options and Available User I/O (LVDS Pairs):
Package Type Decription Pitch (mm)
Size
(mm)
GW5AT-60
(True LVDS Pairs) Transceivers MIPI D-PHY Hardcore MIPI C-PHY Hardcore PG484A
PBGA Wire Bond 1.0 23 x 23 297(143) 4
-
-
UG225 UBGA Wire Bond 0.8 13 x 13 113(53) 4
RX/TX
4 data lanes
1 clock lane
RX/TX
3 data lanes
1 clock lane
UG324S UBGA Wire Bond 0.8 15 x 15 198(98) 4
-
-
GW5AT-75 Package Options and Available User I/O (LVDS Pairs):
Package Type Decription Pitch (mm)
Size
(mm)
GW5AT-75
(True LVDS Pairs) Transceivers MIPI D-PHY Hardcore MIPI C-PHY Hardcore
UG484
UBGA
Wire Bond
0.8
19 x 19
311(150)
8
RX
8 data lanes
2 clock lanes
GW5AT-15 Package Options and Available User I/O (LVDS Pairs):
Package Type Decription Pitch (mm)
Size
(mm)
GW5AT-15
Transceivers MIPI D-PHY Hardcore MIPI C-PHY Hardcore MG132 MBGA Wire Bond 0.5 8
x 8 53(25) 4
RX/TX
4 data lanes
1 clock lane
RX/TX 3-trios data
CS130 WLCSP Wire Bond 0.4 4.0 x 5.3 53(25) 4
RX/TX
4 data lanes
1 clock lane
RX/TX 3-trios data
Note!
* Tranceivers in PBGA packages support data rates up to 8 Gbps.
* Tranceivers in FCPBGA packages support data rates up to 12.5 Gbps.
* Transceivers in the MBGA package can reach speeds up to 10.3125 Gbps, and
when the rate exceeds 8 Gbps, only on-board interconnects are supported, not
backplane applications.
GW5AR Series Table
Device GW5AR-25 LUT4 23040 REG 23040 Shadow SRAM SSRAM (kb) 180 Block SRAM BSRAM
(kb) 1008 Number of BSRAM 56 Embedded PSRAM(bits)
64M DSP 28 PLLs 6 Global Clock 16 HCLK 16 Transceivers 0 Transceivers Rate N/A
PCle 2.0 0 LVDS Gbps 1.25 DDR3 Mbps 1066 MIPI D-PHY Hardcore
2.5Gbps(Rx/Tx)
4 Data Lanes
1 Clock Lane
ADC 1 Number of GPIO Banks 8 Max. GPIOs 239 Core Voltage Typ. 0.9V/1.0V
--------------------------------------------------------------------------------
Package Options and Availible User I/O (LVDS Pairs):
Package Pitch (mm)
Size(mm)
GW5AR-25
MIPI D-PHY Harcore
UG256P 0.8 14 x 14 178 (86)
RX/TX Configurable
4 data lanes
1 clock lane
Note!
[1] Different packages support different numbers of phase-locked loops, here is
the maximum value.
[2] In addition to the GPIO Bank, it also contains a JTAG Bank with 4 I/Os and a
Config Bank with 1 I/O.
GW5AS Series Table
Device GW5AS-25 GW5AS-138 LUT4 23040 138240 REG 23040 138240 Shadow SRAM SSRAM
(kb) 180 1080 Block SRAM BSRAM (kb) 1008 6120 Number of BSRAM 56 340 Hard-core
Processor Cortex-M4
RiscV AE350_SOC
DSP 28 298 PLLs 6 12 Global Clock 16 16 High-speed Clocks 16 24 LVDS Gbps 1.25
1.25
DDR3 Mbps 1066
1333
MIPI D-PHY Hardcore
2.5Gbps(RX/TX)
4 Data Lanes
1 Clock Lane
2.5Gbps(RX)
8 Data Lanes
2 Clock Lane
ADC
FPGA:1
Cortex-M4:3
2 Number of GPIO Banks 8 6 Max. GPIOs 239 312 Core Voltage Typ. 1.2V 0.9V/1.0V
--------------------------------------------------------------------------------
Package Options and Availible User I/O (LVDS Pairs):
Package Pitch (mm)
Size(mm)
GW5AS-25 GW5AS-138 MIPI D-PHY Harcore UG256 0.8 14 x 14 144(68) -
RX/TX
Configurable
4 data lanes
1 clock lanes
UG324A 0.8 15 x 15 - 222(106)
-
GW5AST Series Table
Device GW5AST-138 LUT4 138240 REG 138240 Shadow SRAM SSRAM (kb) 1080 Block SRAM
BSRAM (kb) 6120 Number of BSRAM 340 DSP 298 PLLs 12 Global Clock 16 HCLK 24
Transceivers 8 Transceivers Rate
270Mbps-
12.5Gbps
PCle 2.0
1,
x1, x2, x4, x8 PCIe 2.0
LVDS Gbps 1.25 DDR3 Mbps 1333 MIPI D-PHY Hardcore
2.5Gbps(RX)
8 Data Lanes
2 Clock Lanes
Hard-core Processor
RiscV AE350_SOC
ADC 2 Number of GPIO Banks 6 Max. GPIOs 376 Core Voltage Typ. 0.9V/1.0V
--------------------------------------------------------------------------------
Package Options and Availible User I/O (LVDS Pairs):
Package Pitch (mm)
Size(mm)
GW5AST-138 FPG676A(FC) 1.0 27 x 27 312(150) PG484A 1.0 23 x 23 297(143) PG676A
1.0 27 x 27 312(150)
Note!
* The number of PLLs supported by different packages is different, here is the
maximum value.
GW5ART-15 Series Table
Device GW5ART-15 LUT4 15120 REG 15120 Shadow SRAM SSRAM (kb) 118.125 Block SRAM
BSRAM (kb) 630 Number of BSRAM 35 PSRAM (units)
2(CM90P)
1(MG132P)
Single PSRAM (bits) 64M NOR Flash (bits) - DSP (27-bit x 18-bit) 28 DSP Lite 12
JPEG Encoder & Decoder
1
PLLs 2 Global Clocks 16 High Speed CLocks 2 Transcievers 4 Transciver Rate
270Mbps-12.5Gbps
PCIe3.0 Hardcore
1, x1, x2, x4, PCIe3.0
LVDS Gbps 1.25 DDR3 Mbps 1333 MIPI D-PHY Hardcore 2.5Gbps(=5.75Gbps, RX/TX),
3-trios data lanes MIPI C-PHY Hardcore 2.5Gbps(=5.75Gbps, RX/TX), 3-trios data
lanes ADC 1 Number of GPIO Banks 4 Max GPIOs 53 Core Voltage 0.9V
Package Options and Available User I/O (LVDS Pairs):
Package Type Decription Pitch (mm)
Size
(mm)
GW5ART-15
Transceivers MIPI D-PHY Hardcore MIPI C-PHY Hardcore CM90P CM Wire Bond 0.5 5.3
x 4.9 23(11) 4
RX/TX
4 data lanes
1 clock lane
-
CM90PF CM Wire Bond 0.5 5.3 x 4.9 23(11) 4
-
RX/TX
3-trios data lanes
CS126P CS Wire Bond 0.4 5.3 x 4.9 23(11) 4
RX/TX
4 data lanes
1 clock lane
RX/TX
3-trios data lanes
MG132P MBGA Wire Bond 0.5 8 x 8 38(18) 4
RX/TX
4 data lanes
1 clock lane
RX/TX
3-trios data lanes
Note!
* Transceivers in the MBGA package can reach speeds up to 10.3125 Gbps, and
when the rate exceeds 8 Gbps, only on-board interconnects are supported, not
backplane applications.
GW5ANT-15 Series Table
Device GW5ANT-15 LUT4 15120 REG 15120 Shadow SRAM SSRAM (kb) 118.125 Block SRAM
BSRAM (kb) 630 Number of BSRAM 35 PSRAM (units) - Single PSRAM (bits) - NOR
Flash (bits) 8M DSP (27-bit x 18-bit) 28 DSP Lite 12 JPEG Encoder & Decoder
1
PLLs 2 Global Clocks
16
High Speed CLocks 2 Transcievers 4 Transciver Rate
270Mbps-12.5Gbps
PCIe3.0 Hardcore
1, x1, x2, x4, PCIe3.0
LVDS Gbps 1.25 DDR3 Mbps 1333 MIPI D-PHY Hardcore 2.5Gbps(=5.75Gbps, RX/TX),
3-trios data lanes MIPI C-PHY Hardcore 2.5Gbps(=5.75Gbps, RX/TX), 3-trios data
lanes ADC 1 Number of GPIO Banks 4 Max GPIOs 53 Core Voltage 0.9V
--------------------------------------------------------------------------------
Package Options and Available User I/O (LVDS Pairs):
Package Type Decription Pitch (mm)
Size
(mm)
GW5ANT-15
Transceivers MIPI D-PHY Hardcore MIPI C-PHY Hardcore
MG132
MBGA Wire Bond 0.5 8 x 8 47(22) 4
RX/TX
4 data lanes
1 clock lane
RX/TX 3-trios data lanes
Note!
* Transceivers in the MBGA package can reach speeds up to 10.3125 Gbps, and
when the rate exceeds 8 Gbps, only on-board interconnects are supported, not
backplane applications.
GW5ANRT-15 Series Table
Device GW5ANRT-15 LUT4 15120 REG 15120 Shadow SRAM SSRAM (kb) 118.125 Block SRAM
BSRAM (kb) 630 Number of BSRAM 35 PSRAM (units) 1 Single PSRAM (bits) 64M NOR
Flash (bits) 8M DSP (27-bit x 18-bit) 28 DSP Lite 12 JPEG Encoder & Decoder
1
PLLs 2 Global Clocks 16 High Speed CLocks 2 Transcievers 4 Transciver Rate
270Mbps-12.5Gbps
PCIe3.0 Hardcore
1, x1, x2, x4, PCIe3.0
LVDS Gbps 1.25 DDR3 Mbps 1333 MIPI D-PHY Hardcore 2.5Gbps(=5.75Gbps, RX/TX),
3-trios data lanes MIPI C-PHY Hardcore 2.5Gbps(=5.75Gbps, RX/TX), 3-trios data
lanes ADC 1 Number of GPIO Banks 4 Max GPIOs 53 Core Voltage 0.9V
--------------------------------------------------------------------------------
Package Options and Available User I/O (LVDS Pairs):
Package Type Decription Pitch (mm)
Size
(mm)
GW5ANRT-15
Transceivers MIPI D-PHY Hardcore MIPI C-PHY Hardcore MG132P MBGA Wire Bond 0.5 8
x 8 32(16) 4
RX/TX
4 data lanes
1 clock lane
RX/TX 3-trios data
Note!
* Transceivers in the MBGA package can reach speeds up to 10.3125 Gbps, and
when the rate exceeds 8 Gbps, only on-board interconnects are supported, not
backplane applications.
GW5AT (Automotive) Series Table
Device GW5AT-138 (Automotive) LUT4 138240 REG 138240 Shadow SRAM SSRAM (kb) 1080
Block SRAM BSRAM (kb) 6120 Number of BSRAM 340 DSP 298 PLLs 12 Global Clock 16
HCLK 24 Transceivers 8 Transceivers Rate
270Mbps-
12.5Gbps
PCle 2.0
1,
x1, x2, x4, x8 PCIe 2.0
LVDS Gbps 1.25 DDR3 Mbps 1333 MIPI D-PHY Hardcore
2.5Gbps(RX)
8 Data Lanes
2 Clock Lanes
ADC 2 Number of GPIO Banks 6 Max. GPIOs 312 Core Voltage Typ. 0.9V/1.0V
--------------------------------------------------------------------------------
Package Options and Availible User I/O (LVDS Pairs):
Package Type Decription Pitch (mm)
Size
(mm)
GW5AT-138
(True LVDS Pairs) Transceivers MIPI D-PHY Hardcore PG484 PBGA Wire Bond 1.0 23 x
23 271(133) 4
RX
8 data lanes
2 clock lanes
PG484FPBGAWire Bond1.023 x 23276(133)4
UG324A UBGA Wire Bond 0.8 15 x 15 142(68) 4
RX
8 data lanes
2 clock lanes
PG484F PBGA Wire Bond 1.0 23 x 23 276(133) 4
RX
8 data lanes
2 clock lanes
Note!
[1] Different packages support different numbers of phase-locked loops, here is
the maximum value.
GW5A (Automotive) Series Table
Device GW5A-25 (Automotive) LUT4 23040 REG 23040 Shadow SRAM SSRAM (kb) 180
Block SRAM BSRAM (kb) 1008 Number of BSRAM 56 DSP 28 PLLs 6 Global Clock 16
High-speed Clocks 16 LVDS Gbps 1.25 DDR3 Mbps 1066 MIPI D-PHY Hardcore
2.5Gbps(RX/TX)
4 Data Lanes
1 Clock Lane
Number of GPIO Banks 8 Max. GPIOs 239 Core Voltage Typ. 0.9V/1.0V
--------------------------------------------------------------------------------
Package Options and Availible User I/O (LVDS Pairs):
Package Pitch (mm)
Size(mm)
GW5AS-25 MIPI D-PHY Harcore PG256 1.0 17 x 17 184(88)
RX/TX
Configurable
4 data lanes
1 clock lanes
UG324F 0.8 15 x 15 223(108)
RX/TX
Configurable
4 data lanes
1 clock lanes
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