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INSTITUTE FOR COMPLEX SYSTEMS




WELCOME TO THE INSTITUTE FOR COMPLEX SYSTEMS

The Institute for Complex Systems (ICS) targets the ever-increasing complexity
of hardware/software systems. Here, the institute considers suitable abstraction
levels, i.e. Virtual Prototypes (VPs) in SystemC for HW/SW systems at the
Electronic System Level (ESL), HW designs in Verilog/VHDL at the Register
Transfer Level (RTL), down to the gate-level. Primary research areas are
verification, debugging, and synthesis, all major problems in Electronic Design
Automation (EDA). We heavily use the RISC-V Instruction Set Architecture (ISA)
in our research work (see e.g. our open-source RISC-V VP++).


ANNOUNCEMENTS

 * We are looking for Student Assistants. If you are interested, please contact
   Prof. Daniel Große.

Johannes Kepler University Linz
Altenberger Straße 69
4040 Linz
Austria Science Park 4, 3rd floor ics-office@jku.at +43 732 2468 4561


NEWS




2024

 * Jan 30, 2024: Daniel Große has been appointed as Program Committee Member of
   the Forum on specification & Design Languages (FDL) 2024.
 * Jan 23-25, 2024: Our works on (i) Verifying embedded graphics libraries
   leveraging virtual prototypes and metamorphic testing and (ii) Towards a
   highly interactive design-debug-verification cycle are presented at the Asia
   and South Pacific Design Automation Conference (ASP-DAC 2024).
 * Jan 16, 2024: Daniel Große has been appointed as Program Committee Member of
   the 4th Workshop on Open-Source Design Automation (OSDA) 2024.


2023

 * Dec 21, 2023: Florian Stögmüller received the third-place Adolf Adam award in
   acknowledgment of his outstanding Master’s thesis. The award winners were
   selected by higher-level school students from schools throughout Upper
   Austria. Congratulations! Based on the results of his master thesis, the
   paper Verifying embedded graphics libraries leveraging virtual prototypes and
   metamorphic testing will appear at the Asia and South Pacific Design
   Automation Conference (ASP-DAC 2024).
 * Dec 19, 2023: Daniel Große has been appointed as Program Committee Member of
   the RISC-V Summit Europe 2024.
 * Dec 14, 2023: Felix Roithmayr successfully completed his Bachelor thesis
   entitled “From Model to Metal – The SUBLEQ microcoded microprocessor
   Goldcrest on the ICEStick1k”. Congratulations!
 * Nov 14-16, 2023: Our works on (i) DSA monitoring framework for HW/SW
   partitioning of application kernels leveraging VPs and (ii) Large-scale
   gatelevel optimization leveraging property checking are presented at the
   Design and Verification Conference Europe (DVCon Europe) 2023 in the research
   track. Moreover, we contribute to the SystemC Evolution Day 2023 with the
   presentation RISC-V VP++: Unlocking the vast Linux ecosystem for Open Source
   RISC-V Virtual Prototypes: From Fast Bootup, VNC, Vector Extension to
   3D-Games.
 * Nov 10, 2023: Our virtual prototype RISCV-VP++ is available now at our ICS
   GitHub. RISCV VP++ allows very fast Linux bootup, VNC, Vector Extension
   (RVV), 3D-game demos, and more! Take a look at the GUI-VP Kit to get a quick
   and easy-to-use starting point for experimenting with RISCV-VP++, Linux and
   interactive graphical applications.
 * Oct 05, 2023: The Call for Papers of the GMM/ITG/GI-Workshop Methoden und
   Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und
   Systemen (MBMV) 2024. Please submit your work!
 * Sep 26, 2023: Moritz Stockinger successfully completed his Bachelor thesis
   entitled “Enhancing a Virtual Prototype with RISC-V Vectoring Extension:
   Implementation and Verification”. Congratulations!
 * Sep 25, 2023: Lucas is featured in the YosysHQ Blog: Community Spotlight -
   WAL. Great article to read. WAL is our open-source Waveform Analysis Language
   available on our ICS GitHub and at wal-lang.org.
 * Sep 25, 2023: Sebastian Windsperger successfully completed his Bachelor
   thesis entitled “Circuit-Based RISC-V Instruction Visualiser”.
   Congratulations!
 * Sep 13-15, 2023: Our work on Enhancing Compiler-Driven HDL Design with
   Automatic Waveform Analysis was presented at the Forum on specification &
   Design Languages (FDL) 2023. Moreover, we contributed to a special session on
   RISC-V with the presentation “Recent Developments in Open-source RISC-V
   Virtual Prototypes: From Vector Extensions, Tracing to 3D-Games”. Finally,
   Daniel Große and Lucas Klemmer gave a tutorial on our Waveform Analysis
   Language (WAL) entitled Get the Most out of Your Waveforms – From
   Non-functional Analysis to Functional Debug via Programs on Waveforms.
 * Aug 24, 2023: Daniel Große has been appointed as Program Committee Member of
   the Design Automation and Test in Europe (DATE) 2024.
 * Jul 07, 2023: Manfred Schlägl successfully completed his Master Thesis on
   “GUI-VP Kit: A RISC-V VP Meets Linux Graphics - Enabling Interactive
   Graphical Application Development”. Congratulations!
 * Jun 07, 2023: Our work on GUI-VP Kit: A RISC-V VP meets Linux graphics -
   enabling interactive graphical application development is presented at the
   ACM Great Lakes Symposium on VLSI (GLSVLSI 2023). GUI-VP Kit is also
   available at our ICS GitHub.
 * Jun 5-9, 2023: Our work on A DSL for visualizing pipelines: A RISC-V case
   study is presented at the RISC-V Summit Europe 2023.
 * May 12, 2023: Daniel Große has been appointed as Topic Co-Chair for
   “Validation, Verification, Debug and Diagnosis” at the European Test
   Symposium (ETS) 2024. Please submit your work!
 * May 02, 2023: Florian Stögmüller successfully completed his Master Thesis on
   “Verifying an Embedded Graphics Library leveraging a RISC-V Virtual Prototype
   & Metamorphic Testing”. Congratulations!
 * Apr 17-19, 2023: Our work on Improving design understanding of processors
   leveraging datapath clustering is presented at the Design, Automation and
   Test in Europe (DATE 2023), our work on Programming language assisted
   waveform analysis: A case study on the instruction performance of SERV is
   presented at the Workshop on Open-Source Design Automation (OSDA 2023) hosted
   at DATE, and we demonstrate WAL: A Language for Automated and Programmable
   Analysis of Waveforms at the University Fair of DATE.
 * Apr 06, 2023: Daniel Große has been appointed as Program Committee Member of
   the Design and Verification Conference in Europe (DVCon Europe) 2023 in the
   inaugural research track.
 * Mar 23-24, 2023: Our works on (i) Fuzz-testing of SpinalHDL designs, (ii) How
   we learned to stop worrying and build a RISC-V VP with only one microcode
   instruction and (iii) Divider verification using symbolic computer algebra
   and delayed don’t care optimization are presented at ITG/GI/GMM-Workshop
   Methoden und Beschreibungssprachen zur Modellierung und Verifikation von
   Schaltungen und Systemen (MBMV 2023).
 * Mar 17, 2023: Daniel Große has been appointed as Co-Program Chair of the
   GMM/ITG/GI-Workshop Methoden und Beschreibungssprachen zur Modellierung und
   Verifikation von Schaltungen und Systemen (MBMV) 2024.
 * Feb 23, 2023: Our book Formal Verification of Structurally Complex
   Multipliers has been published by Springer.
 * Jan 25, 2023: Daniel Große has been appointed as Program Committee Member of
   the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2023.
 * Jan 10, 2023: Our book Verbessertes virtuelles Prototyping has been published
   by Springer.
 * Jan 03, 2023: Daniel Große has been appointed as Program Committee Member of
   the Forum on specification & Design Languages (FDL) 2023.

News Archive

JKU Institute for Complex Systems, Altenberger Straße 69, 4040 Linz, Austria,
Tel.: +43 732 2468 4561 – Imprint