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Submission: On December 19 via api from US — Scanned from DE
Effective URL: https://si2plus.105h.net/
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Submission: On December 19 via api from US — Scanned from DE
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MENU * HOME * ABOUT Company Introduction * UNDERSTANDHETEROGENEOUSINTEGRATION STRUCTURE * TECHNOLOGY Integrated Substrate * WORK WITH SiPlus * IP LICENSINGANDSAMPLE BUILDING * PETITE CONSORTIUM for HETEROGENEOUS INTEGRATION TECHNOLOGY(PCHIT) * NEWS * CONTACT 1. 2. 3. PLATFORM FOR HETEROGENEOUS INTEGRATION LESS IMPACT TO THE ENVIRONMENT REDUCE OVERALL PRODUCT DEVELOPMENT CYCLE TIME Previous Next TECHNOLOGY 2.0D, 2.2D, 2.1D, 2.3D Integrated Substrate Provider No through vias(TSVs, TLVs..) required. No solders required between interposer / substrate / PCB. One Integrated Substrate can replace the combination of silicon interposer and substrate. Meet functional requirements and simplifies the manufacturing logistic. Quick product prototyping. ABOUT US SiPlus is developing system integration technologies and products that meet functional requirement with less impact to the environment. NEWS 2. FIRST BUILDUP SUBSTRATE SYMPOSIUM; BUSS Invited talk Dyi Chung Hu, “Technologies for Heterogeneous Integration in the GAI Era”. 1. IMPACT 2024 CONFERENCE Keynote Speech Dyi Chung Hu, “2.XD Integrated Substrate Solutions for High-Performance Computing”. 3. ECTC 2023 CONFERENCE Chia-Peng Sun, et al., “Optimization of 2.2D Underfill Process by Novel Methodology and Direct Observation of Capillary Underfill Process”. 4. ICEP 2023 CONFERENCE Dyi Chung Hu, et al., “In-situ observation of underfill dispensing process”. L. H. Shen, et al., “Predicting Void Reduction of Flip Chip Package in the Pressure Oven”. 5. WLPS 2023 CONFERENCE Dyi Chung Hu, et al., “Method of doubling the wafer level RDL layers in 2.2D and RDL Substrate”. 6. ECTC 2022 CONFERENCE Dyi Chung Hu, et al., “A Novel Equivalent Model for Underfill Molding Process On 2.2D Structure for High Performance Applications”. 7. CHIP SCALE REVIEW, 2022 MARCH ISSUE Dyi Chung Hu, SR 2022 paper, “2.2D Die last Integrated Substrate for Heterogeneous Integration Applications”. 8. ECTC 2021 CONFERENCE PAPER ON 2.2D Dyi Chung Hu, et. al. "2.2D Die last Integrated Substrate for High Performance Applications". 9. IMAPS 2020 CONFERENCE PAPER ON 2.0D D.C. Hu and James Ho "Methods to Reduce the Hierarchy of Interconnections in Electronic System". WORK WITH SIPLUS * No. 101, Sec. 2, Kung Fu Rd., Hsinchu City 30013, Taiwan Room 720, Innovation and Incubation Hall, National Tsing Hua University * TEL: 0916767301 * EMAIL: eh.chen@si2plus.com Dialing Navigation ABOUT * Company Introduction TECHNOLOGY * Integrated Substrate WORK WITH SIPLUS HETEROGENEOUS INTEGRATION CONSORTIUM NEWS CONTACT © 2019 SIPLUS CO., LTD. ALL RIGHTS RESERVED.｜DESIGNED BY 106H