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1. homeSiemens Digital Industries Software
2. Design Methodology for Building Power Efficient RTL Seminar
On-Demand Webinar
DESIGN METHODOLOGY FOR BUILDING POWER EFFICIENT RTL SEMINAR
Complete Seminar Recording, Slides, and Q&A
Estimated Watching Time: 146 minutes
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Access this Webinar now
The growth of semiconductor industry hinges on the fact that with every new
generation, chips would have higher performance and consume less power. However,
we are witnessing that scaling through Moore’s law does not automatically
translate to efficiency gains in terms of energy anymore. That’s why regardless
of the application area - networking, computation, or storage - power and energy
consumption can make the difference between a differentiated product and a
product that does not meet customer needs. In the 2020 survey by Wilson
Research, power is now the #3 reason for design re-spins. That brings power at
the front and center in silicon design process. It is obvious that we cannot
wait until the very end of their design cycle to try to fix power problems and
it needs to be considered during the architecture and design phase. We need an
effective hardware design methodology to deliver lowest power RTL IP and/or
designs. This seminar will highlight how power and energy metrics and
optimization can predictably deliver the best quality RTL optimized for power.
It will feature a combination of technical sessions and user case studies
delivered by people who have adopted those best practices to build successful
products.
SEMINAR INTRODUCTION AND CUSTOMER CASE STUDIES
This session will provide an overview of the seminar and key learning
objectives. It will introduce a design flow - adopted by companies from ARM to
Cisco – to build energy efficient RTL IP. The session will go over the value of
thinking about power early in the design cycle. Speaker: Anoop Saha
ARM: DECARBONIZING COMPUTE THROUGH ENERGY-EFFICIENT IP DESIGN
The climate crisis is the greatest challenge facing humanity today. As demand
for cloud services and digital technologies grows, reducing their environmental
impact is critical. Technology roadmaps must make decarbonization a priority.
Hardware design has a key role to play. From increasing performance per watt and
eliminating unnecessary compute to unlocking further optimizations,
energy-efficient IP can significantly impact technology’s global carbon
footprint. This presentation highlights the challenges – both real and perceived
– to decarbonization and considers approaches for achieving energy efficiency in
hardware design. Speaker: Arm Inc.: Pierre-Alexandre Bou-Ach
FAST-TRACKING LOW-POWER DESIGN WITH AN EARLY POWER METHODOLOGY
Low-power is a subject of great attention and rightly so. Power can lead to
design re-spins and competitive disadvantage for products. A low-power
methodology from early RTL design to RTL sign-off can simplify
design-for-low-power and also uncover downstream power sign-off issues, avoiding
costly late-stage changes. Learn how a low-power methodology can be established
that treats power as a first-class citizen and ensures the development of energy
efficient IPs that are free of potential power issues which can cause chip
failures. Speaker: Qazi Ahmed
BUILDING POWER EFFICIENT CISCO NETWORK SWITCHES THROUGH POWERPRO GUIDANCE, EARLY
TRACKING AND OPTIMIZATION
Building on their success in reducing power consumption with PowerPro via a
clock gating efficiency gain of 10-20% with vectorless optimization, Cisco's
Udupi Harisharan will discuss the usefulness of other tool features to guide
designers in making effective clock gating decisions and the feeding back of key
power metrics to the design team during RTL development. Speaker: Cisco: Udupi
Harisharan
FAST AND ACCURATE POWER ANALYSIS USING POWERPRO – FROM IP TO SYSTEM
With increasing design complexities targeting ever-shrinking geometries, the
Power Analysis tools are posed with a challenge of estimating power for these
massively large designs with billions of gates with billions of cycles to
estimate power under real workload scenarios. Challenge is that it must be
accurate and has to be done quickly with fewer iterations. In this session, we
are presenting how PowerPro’s enhanced Power Analysis solution and its
integration with Veloce is helping user estimate the Power across the project
development cycle from IP to System level. Speaker: Mohammed Fahad and Mahmud
Ullah
MEET THE SPEAKERS
Arm
PIERRE-ALEXANDRE BOU-ACH
Technical Director, Physical Implementation
Pierre-Alexandre Bou-Ach is a Technical Director at Arm, originally from the
south of France and now based in Trondheim, Norway.
He is helping the different Arm physical implementation teams worldwide with
methodology and EDA strategy aspects, as well as being the physical
implementation technical authority for the Total Compute program.
He started his career at STMicroelectronics inCrolles, France, working on
high-performance Arm Cortex CPU implementations. He then joined Arm in 2013,
working initially in the GPU group, notably as a physical implementation lead on
several Mali GPU products and also as a methodology team lead for GPU physical
design.
Cisco
UDUPI HARISHARAN
Sr. Tech Lead
Udupi Harisharan has worked on Networking Asics for the past 20 years taping out
more than 15 Asics and Leads a team Focused on design and implementation
including Asic Design methodologies involving Soc integration, Power
optimization, Power Analysis and Emulation of the Data center Asics at Cisco.
Siemens EDA
ANOOP SAHA
Sr Manager of Strategy
Anoop Saha manages strategic growth initiatives for Siemens EDA digital design
portfolio - including Catapult High-Level Synthesis and PowerPro. He also
manages outbound and inbound marketing as well as demand generation. Anoop has
20 years experience in the EDA industry in various roles - from development to
marketing, sales and strategy. He is currently working on system level power
modeling, custom hardware accelerators and machine learning in EDA. Anoop earned
his bachelor degree in Computer Science and Engineering from IIT Kanpur, India
and is currently pursuing his Executive MBA from The Wharton School.
Siemens EDA
MAHMUD ULLAH
Low Power Technologist
Mahmud joined Siemens EDA's PowerPro team in September 2021 and has been working
in PowerPro's power estimation areas. Before joining Siemens, Mahmud spent 23
years at Synopsys where he held many management and technical leadership roles
in various sign-off products. He has a BSEE degree from Utah State University,
MSEE and MBA degrees from San Jose State University.
Siemens EDA
MOHAMMED FAHAD
Technical Marketing Engineer
Mohammed Fahad works with Siemens EDA as Technical Marketing Engineer. Fahad has
more than 17 years of work experience in the field of Low Power, CDC and FPGA
based system design. At Siemens EDA, Fahad is responsible for Low Power
technology deployment and proliferation activities across a variety of
Semiconductor customer base.
Siemens EDA
QAZI FAHEEM AHMED
Principal Product Manager for PowerPro
Qazi is the Principal Product Manager for PowerPro low-power platform at Siemens
EDA. He has over 17 years of experience spanning across ASIC/FPGA design and
EDA.
RELATED RESOURCES
White Paper
ARM'S INPUT QUALIFICATION METHODOLOGY USING POWERPRO
This white paper proposes a new automated input qualification methodology that
Arm developed using Siemens EDA’s PowerPro™ software portfolio that performs
various data integrity checks at the IC design build and prototype stage.
White Paper
MACHINE LEARNING APPLICATION FOR EARLY POWER ANALYSIS ACCURACY IMPROVEMENT
Machine Learning application that estimates the switching power of the cells
without needing the SPEF file (SPEF less PA flow). This new ML approach, reduced
the SPEF-less flow’s average cell switching power error from 34% to 8%.
White Paper
LOW-POWER DESIGN IS A CORPORATE MINDSET AT ARM
Low-power is a mindset at Arm, with every team member looking for power saving
opportunities at every design level. From applications to the transistor level,
Arm takes a system-level approach to low-power design.
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