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 1. Home page
 2. Using a System Technology Co-Optimization (STCO) approach for 2.5/3D
    Heterogeneous Semiconductor Integration

White Paper


USING A SYSTEM TECHNOLOGY CO-OPTIMIZATION (STCO) APPROACH FOR 2.5/3D
HETEROGENEOUS SEMICONDUCTOR INTEGRATION

Reading time: 5 minutes

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With the economics of transistor scaling no longer universally applicable, the
industry is turning to innovative packaging technologies to support system
scaling demands and achieve lower system cost. This has led to the system
technology co-optimization (STCO) concept, where a SoC type system is
disaggregated, or partitioned, into smaller modules (also known as chiplets)
that can be asynchronously designed by dispersed teams and then combined into a
larger, highly flexible system using chiplet-based package design, which may
involve 3D packaging.

To learn more about Package Design, visit.

PRODUCTS

Xpedition IC Packaging



RELATED RESOURCES

White Paper


SURVIVING THE THREE PHASES OF HIGH DENSITY ADVANCED PACKAGING DESIGN

The growth of High Density Advanced Packages (HDAP) such as FOWLP, CoWoS, and
WoW is triggering a convergence of the traditional IC design and IC
package-design worlds.

Fact Sheet


PCB AND IC PACKAGING SYSTEM REQUIREMENTS

PCB and IC Packaging System Requirements document defines the minimum
requirements necessary for successful operation of software solutions, including
processor and operating system requirements.

White Paper


A DEEP DIVE INTO HDAP LVS/LVL VERIFICATION

HDAP LVS/LVL verification is an emerging process, and the data required for
“signoff-level” confidence may often be incomplete.







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