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Welcome to the MyHDL Discussion forum!

We're running on the open source Discourse forum software. They are also
providing the hosting for us. Thanks guys! Please this space as a place to talk
about building stuff using MyHDL, best practices, and ideas for d… read more 0
5.5k May 2016 VHDL constant value overflow
Bug
16 3.6k 29d AttributeError: ‘List’ object has no attribute ‘vhd’…I m getting
this error while i want to make a circuit that does the convolution of square
wave and triangular wave …Please suggest me any modifications in this code so
that i will get the desired op

2 109 Mar 18 MyHDL project explorer
Showcase
4 289 Sep 2023 How to use cosimulation on a windows machine?

5 632 Apr 2023 How to get the latest Version of myhdl 2
Support
4 490 Feb 2023 How to get latest version of myhdl?
Support
12 506 Dec 2022 Pull Request Cleanup
Support
1 339 Dec 2022 Initialisation behaviour can be problematic
Showcase
6 451 Nov 2022 Best practice: my conclusion after months of development
Showcase
2 551 Nov 2022 myhdl.AlwaysCombError: sensitivity list is empty
Support
1 485 Nov 2022 Sub module Verilog synthesis error
Support
3 504 Jun 2022 Sign extend bits
Support
2 593 May 2022 Multiple @always_comb needed - why?
Support
35 769 Apr 2022 Signed error with lshift
Support
3 431 Apr 2022 ToVerilogWarning: Output port is read internally:
Enhancement Request
6 611 Apr 2022 Sanity check: Ps/2 Keyboard on an fpga
Support
2 527 Apr 2022 Preserve hierarchy
Support
8 1.1k Apr 2022 MyHDL synthesis support / jupyosys
Showcase
1 1.2k Jan 2022 Trying to create a fifo through a queue

7 615 Jan 2022 How to do cosimulation with a commercial tool?

3 547 Jan 2022 Creating a group of Signals

5 481 Jan 2022 MyHDL Signals inside functions not showing up in VCD

1 472 Jan 2022 Initial block in MyHDL

2 431 Jan 2022 Long integer translation

5 465 Dec 2021 I am implementing single cycle processor, RV32I … i am facing
issues in top module.. file named as ” core.py ”
Support
1 550 Dec 2021 I am having issue, when i am converting myhdl to verilog it gives
me error on list indexing
Bug
0 465 Nov 2021 Is MyHDL a good choice to create BFMs?
FAQ
6 708 Nov 2021 Type mismatch with earlier assignment

3 454 Oct 2021 Variables in VHDL

3 568 Oct 2021







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