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OVERVIEW


MODELSIM

ModelSim simulates behavioral, RTL, and gate-level code - delivering increased
design quality and debug productivity with platform-independent compile. Single
Kernel Simulator technology enables transparent mixing of VHDL and Verilog in
one design.

Watch webinarView fact sheet

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ModelSim Student Edition

Learn more about the current status of ModelSim Student Edition and options
available.

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Key features


NATIVE COMPILED, SINGLE KERNEL SIMULATOR TECHNOLOGY

ModelSim packs an unprecedented level of verification capabilities into a
cost-effective HDL simulator and is ideally suited for the verification of small
and medium-sized FPGA designs – especially designs with complex,
mission-critical functionality.


ADVANCED CODE COVERAGE

Fast time to coverage closure

ModelSim’s advanced code coverage capabilities provide valuable metrics for
systematic verification. Plus, ModelSim’s ease of use lowers the barriers for
leveraging verification resources. All coverage information is stored in the
highly efficient UCDB database. Coverage results can be viewed interactively,
post-simulation, or after a merge of multiple simulation runs.


MIXED HDL SIMULATION

Mixed language simulation

Comprehensive support of Verilog, SystemVerilog for Design, VHDL, and SystemC
provide a solid foundation for single and multi-language design verification
environments. An easy-to-use and unified environment provides FPGA designers the
advanced capabilities they need for debugging and simulation.


INTUITIVE DEBUG ENVIRONMENT

Fast time-to-debug

ModelSim eases the process of finding design defects with an intelligently
engineered debug environment that efficiently displays design data for analysis
and debug of all hardware description languages. A broad set of intuitive
capabilities for Verilog, VHDL and SystemC make it the ideal choice for ASIC and
FPGA design.

ModelSim resources


FEATURED WHITE PAPERS

White Paper


2022 WILSON RESEARCH GROUP FPGA FUNCTIONAL VERIFICATION TRENDS

This report presents those results from the 2022 Wilson Research Group
Functional Verification Study that were focused on the Field-Programmable Gate
Array (FPGA) segment.

White Paper


IMPROVING VERIFICATION PREDICTABILITY AND EFFICIENCY USING BIG DATA

This paper will cover the technology, the metrics, and the process, and it will
explore several techniques enabled by such an infrastructure.

White Paper


VERIFICATION DATA ANALYTICS WITH MACHINE LEARNING

This paper will cover the technology, the metrics, and the process, and it will
explore several techniques enabled by such an infrastructure.

UVM & SystemVerilog


UPCOMING AND ON-DEMAND EVENTS

View all available UVM & SystemVerilog video recordings at the Verification
Academy.

SVA implementation & code examples
all


INTRODUCTION TO SYSTEMVERILOG ASSERTIONS

ON-DEMAND WEBINAR

In this webinar, you will learn how to implement concurrent assertions using
SystemVerilog Assertions (SVA), and gain a deeper understanding of how they can
complement your existing verification methodologies.


Latest industry ASIC & FPGA trends
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WILSON RESEARCH - 2022 FUNCTIONAL VERIFICATION STUDY

ON-DEMAND WEBINAR

Harry Foster highlights the key findings from the 2022 Wilson Research Group
Functional Verification Study, and provides his interpretation and analysis
behind today's emerging trends in ASIC and FPGA design and verification.


Rapid testbench creation
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CREATE A UVM TESTBENCH IN A DAY - REPEATABLE APPROACH

ON-DEMAND WEBINAR

In this webinar, you will learn how the UVM Framework and Questa Verification IP
enables
testbench creation in a day so the team can focus on creating tests and closing
coverage.


Write proxy-driven testbenches
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EASY TEST WRITING WITH A PROXY-DRIVEN TESTBENCH

ON-DEMAND WEBINAR

In this webinar, we'll examine ways to create powerful reusable testbenches by
hiding the signals and providing your test writers with a proxy that lets them
start writing tests immediately.


Do’s and don’ts of UVM sequences
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UVM CODING GUIDELINES - TIPS AND TRICKS

ON-DEMAND WEBINAR

In this webinar, you will learn how to create testbench transactions and
component classes that are easily debugged and reused. Additional rules are
shown for SystemVerilog code to prevent common bugs.


Learn vectors & arrays differences
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TAKING SYSTEMVERILOG ARRAYS TO THE NEXT DIMENSION

ON-DEMAND WEBINAR

In this webinar, you will learn that SystemVerilog has many dynamic data & array
types. You will be shown which ones to choose for scoreboards, sparse memories,
hash arrays, testbenches and more.


Structures for modeling hardware
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SYSTEMVERILOG STRUCTURES AND PACKAGES

ON-DEMAND WEBINAR

In this webinar, learn how you can model hardware registers down to the bit
level, or build complex data types that contain a mix of different elements such
as 4-state logic, 2-state integers, real numbers, and enumerated types.


Extending your transaction classes
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STIMULATING SIMULATING: UVM TRANSACTIONS

ON-DEMAND WEBINAR

In this webinar, you will learn how to create classes for UVM transactions, also
known as sequence items. You will also be shown where are these created and used
in a testbench, and what class should you start with.


Stimulus with virtual sequences
all


STIMULATING SIMULATING 2: UVM SEQUENCES

ON-DEMAND WEBINAR

In this webinar, you will learn to create classes for UVM sequences, containing
one or more transactions, how a test class starts a sequence and how
transactions flow to and from the sequence into the rest of the testbench.


Learn to parse Verilog expressions
all


VERILOG BASICS FOR SYSTEMVERILOG CONSTRAINED RANDOM

ON-DEMAND WEBINAR

In this webinar you will learn the two of the most common issues when constraint
solver results do not match your intent: how Verilog expression evaluation rules
apply and the affect probability has on choosing solution values.


Key additions in UVM 1800.2
all


UVM 1800.2 & THE NEW AND IMPROVED UVM COOKBOOK

ON-DEMAND WEBINAR

In this webinar, you will learn the changes in UVM 1800.2 from UVM 1.2 and 1.1d
so you can be prepared to embrace the new Standard. We'll cover key additions in
UVM 1800.2 and what’s in the new UVM Cookbook.




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VERIFICATION ACADEMY



Verification Academy provides the skills necessary to mature an organization's
functional verification process capabilities, providing a methodological bridge
between high-level value propositions and the low-level details.



View resources

VERIFICATION HORIZONS BLOG



Insight and updates on concepts, values, standards, methodologies, and examples
to assist with the understanding of what advanced functional verification
technologies can do and how to most effectively apply them.



Read blog

VERIFICATION HORIZONS



The Verification Horizons publication provides concepts, values, methodologies
and examples to assist with the understanding of what advanced functional
verification technologies can do and how to most effectively apply them.



View the latest issue