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Form analysis 1 forms found in the DOM
POST /en/search?tx_indexedsearch_pi2%5Baction%5D=search&tx_indexedsearch_pi2%5Bcontroller%5D=Search&cHash=347cd0d96832375fb40fd71d004b4d19
<form method="post" action="/en/search?tx_indexedsearch_pi2%5Baction%5D=search&tx_indexedsearch_pi2%5Bcontroller%5D=Search&cHash=347cd0d96832375fb40fd71d004b4d19">
<div>
<input type="hidden" name="tx_indexedsearch_pi2[__referrer][@extension]" value="">
<input type="hidden" name="tx_indexedsearch_pi2[__referrer][@controller]" value="Standard">
<input type="hidden" name="tx_indexedsearch_pi2[__referrer][@action]" value="default">
<input type="hidden" name="tx_indexedsearch_pi2[__referrer][arguments]" value="YTowOnt994b640f6ea67e4e991c9786e79732c4b4f834f49">
<input type="hidden" name="tx_indexedsearch_pi2[__referrer][@request]"
value="a:3:{s:10:"@extension";N;s:11:"@controller";s:8:"Standard";s:7:"@action";s:7:"default";}3bd21b1cedcde2bb1b612c0b7aa27230ba89a548">
<input type="hidden" name="tx_indexedsearch_pi2[__trustedProperties]" value="a:1:{s:6:"search";a:2:{s:5:"sword";i:1;s:12:"submitButton";i:1;}}167d203c8ebdd89cf05bbc7703adef47ef4a7790">
</div>
<input placeholder="Search for" class="search-box-input form-control" type="text" name="tx_indexedsearch_pi2[search][sword]">
<button class="search-box-button" title="Start search" type="submit" name="tx_indexedsearch_pi2[search][submitButton]" value="">
<span class="icon-icon_search search"></span>
</button>
</form>Text Content
Cookie Policy We use cookies and other tracking technologies to personalize and improve your experience. By continuing to use our website you consent to this. necessary statistics marketing allow cookies allow all! Webinar "Versal ACAP: The processing system interfaces" -register now- * Training * Design * Products * Company * Partner * Career * News * EN * DE * Training * Design * Products * Company * Partner * Career * News 1. Home 2. Training 3. Compact Vitis for Acceleration COMPACT VITIS FOR ACCELERATION Sequential processing or data path speed is a bottleneck in many high-end systems based on CPUs whereas FPGAs provide massive parallel data processing along with optimized data path. A system with CPU and FPGA combination would be an ideal solution by utilizing best of both worlds. But FPGA development is more complex and oft en hard to achieve time-to-market requirements. Xilinx developed a hard- and soft ware-based ecosystem to utilize FPGAs as an application specifi c processing element along with CPU. Xilinx’ unified software environment VITIS off ers the capabilities to translate CPU code into such FPGA kernels. With these techniques FPGA based development is streamlined by staying in high level programming languages and using OpenCL API for application offl oading and data path acceleration. In this course, you will learn how to develop, debug and profi le new or existing C/C++ and RTL applications with Vitis targeting both data center (DC) and embedded applications. You will also learn how to run designs on the Xilinx Alveo accelerator board. The course is focused on: • Building a software application using the OpenCL™ API to run hardware kernels on Alveo accelerator cards • Building a software application using the OpenCL API and the Linux-based Xilinx runtime (XRT) to schedule the hardware kernels and control data movement on an embedded processor platform • Demonstrating the Vitis environment GUI flow and makefile flow for both DC and embedded applications • Describing the Vitis platform execution model and XRT • Describing kernel development using C/C++ and RTL • Utilizing the Vitis analyzer tool to analyze reports • Explaining the design methodology to optimize a design -------------------------------------------------------------------------------- APPLICABLE TECHNOLOGIES * Architecture: Xilinx Alveo accelerator cards, SoCs and ACAPs -------------------------------------------------------------------------------- REQUIREMENTS * Basic knowledge of Xilinx FPGA architecture * Comfort with the C/C++ programming language * Software development flow DATES -------------------------------------------------------------------------------- 01.08.2022 | Freiburg Booking 14.11.2022 | Frankfurt Booking DURATION & FEE -------------------------------------------------------------------------------- Duration: 3 days Fee: 2,100.00 € net per person including detailed training material, beverages during breaks and lunch CONTACT -------------------------------------------------------------------------------- Michael Schwarz +49 (0) 7664 91313-15 E-Mail DOWNLOADS -------------------------------------------------------------------------------- Download document (PDF) MORE TRAININGS IN THIS CATEGORY Versal ACAP: The processing system interfaces - WEBINAR 21.07.2022 Online MicroBlaze Essentials and Workflow - LIVE ONLINE 21.07.2022 Online Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE 25.07.2022 Online Versal ACAP System Architecture 01.08.2022 Stuttgart Compact Versal ACAP for SW Designers 03.08.2022 Freiburg * Route * Contact * Imprint * Privacy Policy * TAC * Career * News * Newsletter * Company +49 (0) 7664 91313-0 Mo - Fr: 08:00 a.m. – 5:00 p.m. send us an email * facebook * YouTube * Twitter * LinkedIn PLC2 Training PLC2 Design