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Skip to content * SERVICES * BLOG * CAREERS * EDUCATION * RESOURCES * CONTACT US Menu * SERVICES * BLOG * CAREERS * EDUCATION * RESOURCES * CONTACT US * SERVICES * BLOG * CAREERS * EDUCATION * RESOURCES * CONTACT US Menu * SERVICES * BLOG * CAREERS * EDUCATION * RESOURCES * CONTACT US FUNCTIONAL VERIFICATION PLANNING AND MANAGEMENT Working with 150+ companies in 30+ countries, we are recognized for our high quality products and customer responsiveness. DISCOVER MORE ABOUT AMIQ CONSULTING We provide our clients with a solid base of expertise in hardware design verification, built since 2003. Our clients operate in industries like automotive, telecommunications, and computer peripherals. We combine a deep knowledge of hardware design verification, languages, methodologies, and tools with extensive project experience to help our clients deliver complex designs on time, within a budget and infrastructure constraints. SERVICES Functional Verification System Level Verification Project Rescue and Ramp-up Verification IP Development and Qualification Coaching Functional Verification We provide ASIC and FPGA functional verification services spanning across the entire coverage-driven verification flow from specification to coverage sign-off. Our consultants have the expertise to work on an entirely new verification project from beginning to end, as well as the skills and flexibility to engage with any critical points in your project. We have extensive experience of all major hardware verification languages (HVLs) such as e-Language and SystemVerilog, and methodologies such as UVM, OVM, VMM, and eRM… Read more System Level Verification Due to the very high clock cycle consumption of System Level Verification, the planning and implementation of the verification process needs to be done carefully. The verification process requires in-depth planning, advanced verification skills like object-oriented language programming (SystemVerilog, C++/SystemC) and methodology awareness (UVM), as well as a creative approach to problem solving. We have the expertise to provide system-level verification services for complex SoCs, involving working with various hardware and software IPs and using specific tools like hardware acceleration and hardware emulati… Read more Project Rescue and Ramp-up We have been successful at rescuing projects that have gone off track. We start by identifying the project bottlenecks. We then define a rescue strategy and implement it. We analyze performance periodically and continue to refine our strategy taking into account all internal and external factors until the project is back on track. Our ramp-up services include infrastructure setup, template creation, methodology/flow definition and implementation, and resource planning. We can also perform interviews to assist with hiring new team members. Read more Verification IP Development and Qualification We can develop verification IPs (VIPs) on demand, for any protocol or function, by using any one of the HVLs (e, SystemVerilog) or assertion languages (SVA, PSL). Normally, the client provides us with the protocol or function specification and we deliver the code, documentation, suites of tests, regression reports and scripts. The deliverables are prioritized according to client’s requirements and schedule in such a way that the integration work can start before the final release of the VIP… Read more Coaching We provide on-site and off-site training services for a broad range of hardware verification languages and methodologies. The training is delivered by senior consultants with comprehensive experience of working on a range of different projects with top companies. Read more SERVICES Functional Verification System Level Verification Project Rescue and Ramp-up Verification IP Development and Qualification Coaching Functional Verification We provide ASIC and FPGA functional verification services spanning across the entire coverage-driven verification flow from specification to coverage sign-off. Our consultants have the expertise to work on an entirely new verification project from beginning to end, as well as the skills and flexibility to engage with any critical points in your project. We have extensive experience of all major hardware verification languages (HVLs) such as e-Language and SystemVerilog, and methodologies such as UVM, OVM, VMM, and eRM… Read more System Level Verification Due to the very high clock cycle consumption of System Level Verification, the planning and implementation of the verification process needs to be done carefully. The verification process requires in-depth planning, advanced verification skills like object-oriented language programming (SystemVerilog, C++/SystemC) and methodology awareness (UVM), as well as a creative approach to problem solving. We have the expertise to provide system-level verification services for complex SoCs, involving working with various hardware and software IPs and using specific tools like hardware acceleration and hardware emulati… Read more Project Rescue and Ramp-up We have been successful at rescuing projects that have gone off track. We start by identifying the project bottlenecks. We then define a rescue strategy and implement it. We analyze performance periodically and continue to refine our strategy taking into account all internal and external factors until the project is back on track. Our ramp-up services include infrastructure setup, template creation, methodology/flow definition and implementation, and resource planning. We can also perform interviews to assist with hiring new team members. Read more Verification IP Development and Qualification We can develop verification IPs (VIPs) on demand, for any protocol or function, by using any one of the HVLs (e, SystemVerilog) or assertion languages (SVA, PSL). Normally, the client provides us with the protocol or function specification and we deliver the code, documentation, suites of tests, regression reports and scripts. The deliverables are prioritized according to client’s requirements and schedule in such a way that the integration work can start before the final release of the VIP… Read more Coaching We provide on-site and off-site training services for a broad range of hardware verification languages and methodologies. The training is delivered by senior consultants with comprehensive experience of working on a range of different projects with top companies. Read more BLOG RECOMMENDED ARTICLES – FEBRUARY 2023 Aurelian Ionel Munteanu Handling threads in SystemVerilog is always a challenge, especially when reset triggers. How to Decouple Threads in SystemVerilog is showing one way of decoupling a Read More RECOMMENDED ARTICLES – JANUARY 2023 Aurelian Ionel Munteanu SystemVerilog/UVM code reuse is reaching the next level. Andrei Vintilă and Sergiu Duda have developed a framework/architecture called Externally Controlled Testbench (aka ECTB), initially presented Read More AMIQ’S EXTERNALLY CONTROLLED TESTBENCH ARCHITECTURE Andrei Vintilă, Sergiu Duda This article is a follow-up on the paper presented at DVCon EU 2022 entitled How creativity kills reuse – A modern take on UVM/SV TB Read More See more RECOMMENDED ARTICLES – FEBRUARY 2023 Aurelian Ionel Munteanu Handling threads in SystemVerilog is always a challenge, especially when reset triggers. How to Decouple Threads in SystemVerilog is showing one way of decoupling a Read More RECOMMENDED ARTICLES – JANUARY 2023 Aurelian Ionel Munteanu SystemVerilog/UVM code reuse is reaching the next level. Andrei Vintilă and Sergiu Duda have developed a framework/architecture called Externally Controlled Testbench (aka ECTB), initially presented Read More AMIQ’S EXTERNALLY CONTROLLED TESTBENCH ARCHITECTURE Andrei Vintilă, Sergiu Duda This article is a follow-up on the paper presented at DVCon EU 2022 entitled How creativity kills reuse – A modern take on UVM/SV TB Read More See articles INDUSTRIES Home appliances Internet of Things Telecommunications Automotive Green energy management Home appliances We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. Internet of Things We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. Telecommunications We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. Automotive We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. Green energy management We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. INDUSTRIES Home appliances Internet of Things Telecommunications Automotive Green energy management Home appliances We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. Internet of Things We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. Telecommunications We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. Automotive We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. Green energy management We combine a deep knowledge of hardware design verification domain, languages, methodologies and tools with extensive project experience to help companies deliver complex designs on time and within budget and infrastructure constraints. Since the company was established in 2003, we have built up a solid base of expertise in pre-silicon hardware verification and a strong reputation among our clients in the automotive, telecommunications, and computers and peripherals industries. Our core values of passion, responsibility, quality and determination – have guided our growth and the expansion of our service portfolio…. CAREERS @AMIQ CONSULTING JUNIOR VERIFICATION ENGINEER We are looking for a Jr. Verification Engineer with good electronics background and practical object-oriented software knowledge to be trained for the functional hardware verification Read More See more JUNIOR VERIFICATION ENGINEER webdev We are looking for a Jr. Verification Engineer with good electronics background and practical object-oriented software knowledge to be trained for the functional hardware verification Read More See more RESOURCES WEB BOOKSHELF PAPERS CHEATSHEETS ARTICLES WEB Design & Verification Blogs Industry Blogs Tutorials Verification Forums Tools Design & Verification Blogs Blog | AMIQ Consulting AMIQ – Recommended Articles Every month AMIQ compiles a list of recommended articles to be read by a Verification Engineer. The sources are listed bellow. Verification Gentleman A blog about SystemVerilog and e. Verilab – Blog Technology peanut butter and maple syrup. | CFS Vision | Everything you need to know about digital design functional verification Website dedicated to digital design functional verification. Blog with tips and tricks when programming in SystemVerilog and ‘e’. Free components and utilities. Verilog Pro – Verilog and Systemverilog Resources for Design and Verification Verilog and SystemVerilog Resources for Design and Verification ClueBlog – ClueLogic Test and Verification Safety Security TVS provide test and verification services that help companies develop products that are fit for purpose safe and secure. GO 2 UVM – for VLSI Designers » ..your most dependable Verification support desk Blog | Arrow Devices Welcome to our blog section! Munjal The Mystery… Verification Blog See more links Industry Blogs Blogs | Intel® Software Alexandru Voica – Technology peanut butter and maple syrup. Technology peanut butter and maple syrup. EE Times | Electronic Engineering Times | Connecting the Global Electronics Community EE Times connects the global electronics community through news analysis education and peer-to-peer discussion around technology business products and design Welcome to EDACafe the Leading EDA Portal EDACafe.com delivers the latest EDA industry commentary news product reviews articles events and resources from a single convenient point. We provide our users a constantly updated view of the entire world of EDA that allows them to make more timely and informed decisions. Semiconductor Engineering .:. Deep Insights For Chip Engineers Research & Development – Technologies & Strategies That Enable Research & Development Semiconductor Industry Blog | ChipEstimate.com ChipEstimate.com provides the world’s largest catalog of semiconductor IP cores. Search over 200 of the world’s largest IP suppliers and foundries. Find semiconductor IP white papers EDA videos technical articles and more. Systems Design Engineering: simplifying the complex task of designing and developing semiconductors. On-line community providing technology information analysis commentary and an online forum for chip architects and engineers designing and developing semiconductors. Deep Insights for Chip Architects and Engineers Sondrel IC Design Blog IC Design Blog posts on verification DfT Physical Implementation and Analog & Mixed Signal JB Systems Tech • Engineering and Media Company Engineering and Media Company Invionics – Accelerating SystemVerilog Verilog and VHDL Design Automation With the Invio Platform you can build any custom EDA tool for SystemVerilog/Verilog VHDL & UPF using intuitive APIs AMS/UVM libraries built-in packager Practical Chip Design | EDN See more links Tutorials World of ASIC If you are in ASIC or FPGA design then this is the page you should visit here you will find tutorials on Verilog SystemVerilog VERA Digital Electronics SystemC Specman Academy Courses | Verification Academy – Universal Verification Methodology Learn C++ Verilog Online Help Verilog online reference guide verilog definitions syntax and examples. Mobile friendly Neso Academy: Digital Electronics Micro-Lectures A Series of micro-lectures which will make you master in Digital Electronics. No previous knowledge is required to start this course. Each and every topic is… git – the simple guide – no deep shit! What is version control? | Atlassian Git Tutorial Google’s Python Class | Python Education | Google Developers Assorted educational materials provided by Google. Git – Tutorial Student Reviews for Online Courses & Tutorials | CourseDuck Verification Forums Forums: All Topics | Verification Academy The Designer’s Guide Community Forum – Analog Functional Verification A source of in-depth information about the art of circuit simulation and modeling for analog RF and mixed-signal designers. Accellera Systems Initiative Forums Connect with standards experts in the Accellera Systems Initiative forums. Engage with them by posting your questions comments and opinions. Cadence Community – Functional Verification Shared Code Forums Cadence Community – Functional Verification Forums SemiWiki.com Semiconductors Semiconductor Design Semiconductor manufacturing Semiconductor IP EDA Software FPGA SoCs IoT Mobile Devices Semiconductor Stocks Microcontrollers Programmable Devices PLDS Semiconductor Jobs EDA Jobs Tools Edit code – EDA Playground Edit save simulate synthesize SystemVerilog Verilog VHDL and other HDLs from your web browser. Wavedrom – Digital timing diagram everywhere Flowchart Maker & Online Diagram Software diagrams.net is free online diagram software for making flowcharts process diagrams org charts UML ER and network diagrams Regex Tester and Debugger Online – Javascript PCRE PHP Regular Expression Tester with highlighting for Javascript and PCRE. Quickly test and debug your regex. BOOKSHELF Digital Circuit Verification Digital Circuits and System Design Programming Free PDF Books Digital Circuit Verification Assertion-Based Design (Information Technology: Transmission Processing & Storage) https://www.amazon.com/ Creating Assertion-Based IP (Integrated Circuits and Systems) https://www.amazon.com/ SystemVerilog Assertions Handbook, 3rd Edition … for Dynamic and Formal Verification (SystemVerilog Assertions, SystemVerilog Assertions Handbook) https://www.amazon.com/ Assertion-Based Design (Information Technology: Transmission Processing & Storage) https://www.amazon.com/ ESL Models and their Application: Electronic System Level Design and Verification in Practice (Embedded Systems) https://www.amazon.com/ Advanced Formal Verification https://www.amazon.com/ See more books Digital Circuits and System Design Advanced FPGA Design: Architecture, Implementation, and Optimization https://www.amazon.com/ The MicroZed Chronicles – Using the Zynq 101: Complete First Year https://www.amazon.com/ The MicroZed Chronicles – Using the Zynq 101: Second Year https://www.amazon.com/ The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc https://www.amazon.com/ High-Level Synthesis Blue Book https://www.amazon.com/ High-Level Synthesis: from Algorithm to Digital Circuit https://www.amazon.com/ See more books Programming Why Programs Fail: A Guide to Systematic Debugging https://www.amazon.com/ The C++ Programming Language: Special Edition (3rd Edition) https://www.amazon.com/ Programming Language Pragmatics, Third Edition https://www.amazon.com/ Refactoring: Improving the Design of Existing Code https://www.amazon.com/ The Pragmatic Programmer: From Journeyman to Master https://www.amazon.com/ Design Patterns: Elements of Reusable Object-Oriented Software https://www.amazon.com/ See more books Free PDF Books FPGAs!? Now What? – Learning FPGA Design with the XULA Board https://www.amazon.com/ FPGAs for Dummies – 2nd Intel Special Edition https://www.amazon.com/ Introducing the Spartan 3E FPGA and VHDL https://www.amazon.com/ Free Range VHDL. The no-frills guide to writing powerful code for your digital implementations https://www.amazon.com/ PAPERS 2021 2019 2018 2016 2015 2014 2021 DVCON US 2021 OFC – OPEN-SOURCE FRAMEWORK FOR CO-EMULATION USING PYNQ AUTHORS: * Ioana Cătălina Cristea * Dragoș Dospinescu SPEAKERS: * Ioana Cătălina Cristea Functional verification using co-emulation has seen a growing trend due to its main advantage: testbench acceleration. Co-emulation requires two main things: (1) a connection between the host machine running the testbench and the hardware platform where the design is synthesized, and (2) a software component for interacting with the design. Most currently available solutions for achieving a complete co-emulation environment are proprietary. This paper describes an Open-source Framework for Co-emulation (OFC) used for communication between a UVM-SystemVerilog testbench and a design emulated on the FPGA logic of a PYNQ board. The OFC framework is split into two main components: a TCP socket-based client-server connection and a Python component that interacts with the FPGA using the API provided by Xilinx for the PYNQ board. Owing to its modular implementation, the two components can be used either together or separately, depending on the user’s needs. PaperSlides Video Blog See more papers 2019 DVCON US 2019 FUNCTIONAL COVERAGE FOR SYSTEMC (FC4SC) AUTHORS: * Dragos Dospinescu SPEAKERS: * Dragos Dospinescu AMIQ Consulting developed the FC4SC library to complement existing C++ and SystemC libraries with the coverage collection that at the center of any modeling and verification project. Functional coverage lies at the core of semiconductor functional verification as the primary metric to assess quality and track the progress of the entire verification process. FC4SC provides mechanisms for functional coverage definition, collection, and reporting. It can be used in any application compliant with the C++ standard, starting with C++11, including SystemC models. The primary use for the library is to measure the level of exercise of C++/SystemC verification models or C++ applications, checking which features were tested and which parameters were used during the test runs. Verification engineers can augment an existing C++/SystemC project with functional coverage to assess the quality and diversity of test suites. With this library, SystemC/C++ projects have an accurate way to track level of feature exercise and, therefore, the overall verification progress. The FC4SC library is designed to interoperate with other tools and technologies, providing an application programming interface (API) that closely resembles functional coverage definition and usage defined by the IEEE 1800-2017 SystemVerilog standard. The collected data is saved in the Accellera Unified Coverage Interoperability Standard (UCIS) format for future interoperability with other coverage tools. Users can generate reports showing coverage holes, partially covered coverage bins, and other coverage analysis metrics. Paper Blog See more papers 2018 DVCON EUROPE 2018 PORTABLE STIMULUS DRIVEN SYSTEMVERILOG/UVM VERIFICATION ENVIRONMENT FOR THE VERIFICATION OF A HIGH-CAPACITY ETHERNET COMMUNICATION ENDPOINT DVCON EUROPE 2018 PRESENTATION AUTHORS: * Andrei Vintila SPEAKERS: * Andrei Vintila 6.1 Portable Stimulus Driven SystemVerilog/UVM Verification Environment for the Verification of a High-capacity Ethernet Communication Endpoint The scope of this paper is to present the steps taken and the challenges faced when using Portable Stimulus(PSS) as an abstraction layer on top of a SystemVerilog/UVM verification environment. The goal is the verification of a highly configurable, high-speed, communication endpoint, covering complex network scenarios and system-level corner cases. PSS is used in conjunction with SystemVerilog/UVM to increase verification efficiency by avoiding “scenario flooding” and keep a tight control of the verification space. All stimuli are defined in the test-bench and they are used to construct directed/random scenarios by utilizing a PSS generation model. The flow of the project in this case requires the SV/UVM VE to keep up with the guidelines for reusability while having an architecture that is compliant with the PSS mechanics of scenario generation. The paper addresses the possible issues and good practices discovered while implementing this verification strategy. PaperSlides Blog See more papers 2016 DVCON EUROPE 2016 YET ANOTHER MEMORY MANAGER (YAMM) AUTHORS: * Andrei Vintila * Ionut Tolea SPEAKERS: * Andrei Vintila Yet Another Memory Manager (YAMM) is a SystemVerilog library that provides support for memory based operations: * Buffers can be allocated following 6 allocation modes with any granularity or address alignment * Buffers can be inserted by user (non-overlapping) * Buffers can be deallocated either by address or by handle * Buffers can be searched for in the memory space by address or by handle * Buffers support payload, which can be assigned by the user, randomly generated, read and compared. * Implements a fast buffer search algorithm Beside these features YAMM provides debug facilities (e.g. memory map dump, usage statistics) and it is easy to integrate it with existing verification environments. PaperSlides Blog See more papers 2015 SNUG GERMANY 2015 SYSTEMVERILOG ASSERTIONS VERIFICATION WITH SVAUNIT AUTHORS: * Ionut Ciocirlan * Andra Radu SPEAKERS: * Ionut Ciocirlan SystemVerilog Assertions(SVA) play a central role in functional verification of protocols, encompassing feature checking and coverage. In order to benefit from assertion advantages (fast, synthesizable, nonintrusive, coverable), we must verify that they pass or fail as described by the protocol specification. In turn this requires to implement the sequences of stimuli that properly trigger the assertion (making it pass or fail) and checks to ensure its correct behavior under the given conditions. We developed the SVAUnit framework with three objectives in mind: * decouple SVA test logic from SVA definition * simplify the creation of stimuli/checkers that validate the SVA * simplify test and stimuli maintenance SVAUnit is a simulator independent, UVM compliant package that combines the unit testing paradigm of the software world with the powerful feature of assertions from SystemVerilog. PaperSlides Blog See more papers 2014 DVCON EUROPE 2014 ALGORITHM VERIFICATION WITH OPEN SOURCE (OCTAVE) AND SYSTEMVERILOG AUTHORS: * Daniel Ciupitu * Andra Radu SPEAKERS: * Daniel Ciupitu Verification of high computational algorithmic RTL (e.g. digital signal processing) requires complex mathematical models that are hard to implement and slow to run in any of the existing hardware verification languages. Using numerical computing languages (e.g. Octave, Matlab) to code these models will dramatically speed up the verification sign-off by reuse of mathematical functions (e.g. predefined DSP functions) that are already verified. This also has a low risk of algorithm implementation bugs and guarantees optimal implementation for maximum simulation performance. This paper illustrates typical usage of external mathematical models inside the verification environment using SystemVerilog as the verification language and Octave, an open source sibling of Matlab, as the numerical modeling language. Slides Blog See more papers CHEATSHEETS The following CheatSheets are very useful… The following CheatSheets are very useful… SV Cheatsheet Data Types Casting Classes Operators Package Processes Verification Features Design and Verification Blocks SVA Cheatsheet SystemVerilog Assertions SVA Syntax Go to Cheatsheets ARTICLES 2021 2020 2019 2018 2017 2016 2021 RECOMMENDED ARTICLES – DECEMBER 2022 AMIQ is a constant presence at DVCon Europe conference (both AMIQ Consulting and AMIQ EDA). If you haven’t been able to attend the conference or you’ve missed one presentation which was of interest for you, go ahead and read the highlights from our perspective. The highlights article is a joined effort of my colleagues and gives you the pulse from our verification community: Highlights of DVCon EU 2022 In design and verification we often use these two terms: latency and throughput. Here is a short article from Cadence to clarify on their meaning: Understanding Latency versus Throughput Verifying status registers in an RTL design might get tricky. You normally need to consider a so called grey area/zone verification, where the expected value is not always the last update one. Cristian Slav, has detailed for e-language on how to use the built in features of vr_ad register model in order to achieve this kind of verification. Read more in his article: The Hidden Feature of vr_ad: Gray Zone Comparison For those of you using GIT, here is a short article explaining why you should use the git rebase command: Git Rebase Explained This is the last recommended article for 2022. Change and unrest seems to define the current world. I challenge you to find the source of peace so that it may settle inside you and from there to radiate to the people around you and to the whole world. The world can rest and find peace only if every one of us, starting with myself becomes thankful, joyful, humble, faithful, merciful, forgiving, caring and loving. I wish you a Merry Christmas and a Happy New Year. Enjoy your holidays. See you in 2023! See more articles 2020 RECOMMENDED ARTICLES – DECEMBER 2020 Specman and e-language abound in features, some of them are well known some others less known. In my last article, I focus on a less known feature which can be called as string templates We come closer to ending a tumultuous 2020. Literally, the entire world has been challenged to rethink its priorities and values, given the pandemic situation. I hope and pray for a wiser, happier, and fearless 2021. I wish you all a Merry Christmas and a Happy New Year! Enjoy the Holidays! See more articles 2019 RECOMMENDED ARTICLES – DECEMBER 2019 In early 2018, AMIQ released a new library called FC4SC (Functional Coverage for SystemC). The community responded in a positive manner and started to evaluate it and asked for improvements. Late this year, the library has been donated to Accellera in order to fill the functional coverage gap from the SystemC world. More on the reasoning behind the library and its future in this article: AMIQ Consulting Contributes C++ Coverage Library to Accellera Adam Rose, from Verilab, wrote a paper in the form of enhancement proposals for the SystemVerilog language standard. He looked at Python and C++ and tried to borough concepts and apply them to SystemVerilog. In this new SystemVerilog language quest (anonymous classes, introspection, decoration), he described how code constructs like uvm_macros, uvm_factory, constraints and functions would morph into a different kind of code constructs and not only. I think the final paragraph summarizes the goal of the paper: > In many ways, these enhancements simply bring SystemVerilog up to date with > recent > developments in programming languages. By using them, Verification engineers > will be able > to enhance their productivity by writing more concise, modular and > maintainable code. This is the last article for 2019, thus, I take the chance to wish you a Merry Christmas and hope, we all contribute to a better, safer and peaceful new year. Happy New 2020! Enjoy the holidays! See more articles 2018 RECOMMENDED ARTICLES – DECEMBER 2018 Sergiu Duda from AMIQ has put a lot of effort into creating a high quality article on the non-trivial topics of High Level Synthesis and Deep Learning. The later, is not found in the everyday terminology of a verification engineer. Deep learning is just a flavour of a bigger part called Machine Learning which in its turn is part of the bigger, Artificial Intelligence. I do think you will get more meaning out of this topic after spending your time on reading his article: How to Implement a Convolutional Neural Network Using High Level Synthesis Since 2018 is coming to an end and we are days apart from Christmas, I take the chance and wish you a Merry Christmas and hope that the new year brings joy and happiness to all of us. Enjoy the holiday time! See more articles 2017 RECOMMENDED ARTICLES – DECEMBER 2017 CFSVision continues the SystemC tutorial with an indepth explanation of the signal channels: Learning SystemC: Learning SystemC: #005 Signal Channels. PSS starts to be more and more present on verification blogs. Mike Bartley from T&VS and Sharon Rosenberg from Cadence co-edited Portable Stimulus Specification (PSS) and the Reuse Revolution. Giselquist Technologies presents how to build a simple logic PLL. This article helps you understand how logic PLLs work, which is important if you need to verify clock generators or clock recovery blocks. AMIQ released a second version of the Open Source CoverageLens application. The new release extends the UCIS database inspection capabilities, as described in CoverageLens 2.0 Release article. We wish you Happy Holidays! and a 2018 full of accomplishments and happiness! See more articles 2016 RECOMMENDED ARTICLES – DECEMBER 2016 Often, it happens that the information about a Design Under Test (DUT) or about its verification is being organized in the form of a table like structure (configurations, registers, operation modes, traffic types, etc.). Imagine if you could automatically create bits of code from an Excel table. How awesome is that! E-language is now able to do just that. The power of the in_table construct is now doubled if combined with the e-language macros table_row and table from file with. Check out the details in Cadence’s article: Creating Code from Tables. AMIQ wrote a series of articles with the goal of educating graduates/engineers about WHAT does it mean to be a Verification Engineer and HOW you can become a Verification Engineer. Daniel Ciupitu, from AMIQ, continued the series answering the WHY question: AMIQ Blog: To be or not to be a Verification Engineer. Since holiday season is close-by, I wish you Merry Christmas and all the best during 2017! See more articles RESOURCES Web resources Amiq Consulting has been collecting extensive resources for the design and verification community. Web resources include Design & Verification Industry Blogs and Forums, Tutorials, and Tools. Browse Bookshelf A list of great programming books/ ebooks from our functional verification engineers to anyone interested in learning more about digital circuit and system design. You can access these books for free download with full text, or buy them on Amazon. Browse Cheatsheets Browse through the SystemVerilog and SystemVerilog Assertions cheatsheets whenever you have syntax questions. You can easily navigate through the cheatsheets, filtering by Data Types and other criteria. Browse Grammars The following grammars have been generated from SystemVerilog LRM 2012 (IEEE Std 1800TM-2012) and VHDL LRM 2008 (IEEE Std 1076TM-2008). You can browse the grammars here, or you can download the HTML grammars from the GitHub repository. Browse Papers Access for free all the papers our colleagues put together in PDF format, along with the presentations from various international conferences on design verification. Browse GET IN TOUCH WITH AMIQ CONSULTING I understand that this form collects my name and email so I can be contacted. For more information, please check our Terms and Conditions. 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