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Skip to main content Open menu Close menu Tom's Hardware Tom's Hardware Search Search Tom's Hardware RSS US Edition UK US Australia Canada * * Reviews * Best Picks * Raspberry Pi * CPUs * GPUs * News * Coupons * More * Newsletter * PC Components * SSDs * Motherboards * PC Building * Monitors * Laptops * Desktops * Cooling * Cases * RAM * Power Supplies * 3D Printers * Peripherals * Overclocking * About Us Forums Trending * Zen 5 * Intel CPU Instability Issues * Ryzen 9000 Launch Delayed * What is an AI PC * Copilot+ PCs 1. Tech Industry JAPANESE SCIENTISTS DEVELOP SIMPLIFIED EUV SCANNER THAT CAN MAKE PRODUCTION OF CHIPS CONSIDERABLY CHEAPER News By Anton Shilov published yesterday OIST's simplified EUV litho system uses two mirrors instead of six. * * * * * * * Comments (3) When you purchase through links on our site, we may earn an affiliate commission. Here’s how it works. (Image credit: ASML) Professor Tsumoru Shintake of the Okinawa Institute of Science and Technology (OIST) has proposed an all-new and greatly simplified EUV lithography tool that is cheaper than those developed and made by ASML. If the device hits mass production, it could reshape the chipmaking equipment industry, if not the whole semiconductor industry. The new system uses only two mirrors in its optical projection setup, a significant departure from the conventional six-mirror configuration. The challenge of such an optical system is that it involves aligning these mirrors in a straight line, which ensures that the system maintains high optical performance without the usual distortions associated with EUV light. The new optical path allows more than 10% of the initial EUV energy to reach the wafer, compared to about 1% in standard setups, an improvement which is a major breakthrough. (Image credit: Okinawa Institute of Science and Technology) Professor Shintake's team solved two major challenges in EUV lithography: preventing optical aberrations and ensuring efficient light transfer. OIST's 'dual-line field' method illuminates the photomask without interfering with the optical path, which minimizes distortions and enhances image precision on the silicon wafer. One of the key advantages of this minimalist design is that it enhances reliability and reduces maintenance complexities. Another advantage of this EUV lithography tool design is a drastic reduction of its power consumption. Thanks to the optimized optical path, the system operates with an EUV light source of just 20W, leading to a total power consumption of less than 100kW. In contrast, traditional EUV lithography systems often require over 1MW of power. Because of lower power consumption, the new litho system does not require a sophisticated and expensive cooling system. LATEST VIDEOS FROM tomshardwareTom's Hardware (Image credit: Okinawa Institute of Science and Technology) The performance of this new system has been rigorously verified using optical simulation software, confirming its capability for producing advanced semiconductors. The technology's potential has led to a patent filing by OIST, indicating readiness for commercial deployment. OIST is committed to advancing its EUV tool design further, aiming to bring it to practical application. The institute sees this innovation as a vital step toward solving global challenges, such as the costs of chip production and power consumption of semiconductor fabs, which affect the environment. The economic implications of this invention are promising. The global EUV lithography market is expected to grow from $8.9 billion in 2024 to $17.4 billion by 2030. With this simplified design of EUV tools, the industry could adopt more EUV systems in the coming years. However, it is unclear how close OIST is to commercialization of its tool. STAY ON THE CUTTING EDGE: GET THE TOM'S HARDWARE NEWSLETTER Get Tom's Hardware's best news and in-depth reviews, straight to your inbox. Contact me with news and offers from other Future brandsReceive email from us on behalf of our trusted partners or sponsors By submitting your information you agree to the Terms & Conditions and Privacy Policy and are aged 16 or over. Anton Shilov Social Links Navigation Contributing Writer Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends. More about tech industry Intel reportedly gave up a chance to buy a stake in OpenAI in 2017 Imec patterns first logic and DRAM transistors using High-NA litho tools Latest Keychron K2 HE Special Edition Review: Mid-Century Magnetic See more latest ► TOPICS EUV ASML See all comments (3) 3 Comments Comment from the forums * edzieba Reading the paper, this comes with a few heavy caveats: - only 0.2 NA, with a 0.3 NA version being proposed but requires a curved surface photomask to be fabricated (not a trivial task). High-NA EUV is 0.5 NA, and 'standard' EUV is 0.33 NA. - 10m x 26mm field size. Even the 'small' field of TSMV's high-NA EUV machines is 16.5x26, and 'standard' EUV is 33x26mm. - all-aspheric optics - has not been tested in a physical system So the technique is both lower resolution than both standard and high-NA EUV, a much smaller reticule size than even high-NA EUV, and may require custom 2D curved masks and pellicles requiring new fabrication techniques compared to existing masks and pellicles (as if EUV pellicles weren't already enough of an issue).. It also requires fabrication of perforated aspheric Bragg mirrors, which is nontrivial. Reply * dehjomz So should ASML be worried as we enter the Angstrom era, or is this tech not for 18A, 14A and below, but rather, 3nm, 4nm ? Reply * Rinko_x_7 > dehjomz said: > So should ASML be worried as we enter the Angstrom era, or is this tech not > for 18A, 14A and below, but rather, 3nm, 4nm ? Well, using the Rayleigh criterion equation, CD = k1 * λ / NA, even if they do achieve a k1 factor of 0.25 (which is the physical limit) and an EUV wavelength of 13.5nm, they would achieve a critical dimension of 16.875nm if they achieve 0.2NA and 11.25nm if they achieve 0.3NA. Reply * View All 3 Comments MOST POPULAR New Linux kernel attack slips past modern defenses — SLUBStick boasts a 99% success rate Tulip Creative Computer runs MicroPython, targeted at musicians, for only $59 — its open-source nature means you can make your own or just run the software WD announces enterprise 128TB SSD, 8TB SD cards, and a 16TB external SSD at FMS 2024 Nvidia accused of scraping ‘A Human Lifetime’ of videos per day to train AI This 1980s inspired 3D printed Raspberry Pi laptop is built around a Pico-powered mechanical keyboard Micron announces industry first PCIe Gen6 SSD, claims 26GB/s transfer speed Japanese scientists develop simplified EUV scanner that can make production of chips considerably cheaper Intel releases extended warranty details for 13th and 14th-gen chips, list includes Core i5, i7, and i9 processors Samsung mass produces 'world's thinnest' LPDDR5X Entry-level RDNA 3 RX 7400, RX 7300 graphics cards purportedly coming soon Gaming mini-PC looks like a laptop without a screen — AtomMan G7 Ti packs Core i9-14900HX CPU, RTX 4070 Mobile GPU, and up to 96GB RAM Tom's Hardware is part of Future US Inc, an international media group and leading digital publisher. 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