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IP-SOC DAYS 2023
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On Demand Webinars
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Protocol Agnostic Die-to-Die Connectivity for Chiplets and HPC
by OpenFive IMG CXT GPU IP Launch Keynote
by Imagination Technologies Group Ltd. Energy-efficient AI workload partitioning
on multi-core systems
by Mirabilis Design Inc. From timing-margins to cache-misses in advanced SOCs
by proteanTecs Defending the Cloud: PCIe and CXL Data Security for
High-Performance Computing
by Synopsys, Inc.

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Now Open !!
Home Exhibition

When : April 24th, 2023


Where: Hyatt Regency Santa Clara
5101 Great America Parkway, Santa Clara, CA



Join D&R IP SoC Silicon Valley 23 !!        A worldwide connected Event !!


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D&R IP-SoC Silicon Valley 2023 Day is the unique worldwide Spring event fully
dedicated to IP (Silicon Intellectual Property) and IP based Electronic Systems.

IP-SoC providers, the seed of innovation in Electronic Industry, are invited to
highlight their latest products and services and share their vision about the
next innovation steps in the Electronic Industry.

IP consumers can view at a glance the latest Technology trends and exciting
Innovative IP/SoC products. Through a global view, Electronic systems leaders
may identify disruptive innovation leading to new market segment growth.

Registration and Exhibition installation opens at 7 am. Event closes at 5 pm.

Watch Now >>
 * To join the event, you need to be registered. If not yet done, Register Now !

This year will also be the celebration year of D&R 25th anniversary

Thus in a welcome session, gurus from various IP business fields will deliver
their vision about the past quarter of century of IP business and give their
prediction about the trends for the next decade.
 * Asic Designer session
 * Soc Solutions
 *   -

8.30 am
Keynote talk

Chairperson: Gabriele Saucier, D&R
Gabrièle Saucier
CEO
Design and Reuse


About me
Welcome to D&R IP SOC community

Gordon Harling
CEO
CMC Microsystems


About me
Accelerating Innovation with Open Hardware

 
Break
9.40 am
Analog and Memory IP

Chairperson: Mahesh Tirupattur , Analog Bits Inc.
Julian Jenkins
CTO
Perceptia Devices


About me
Integrating RF PLLs into Complex SoC to support 5G and WiFi Radios

Rounak Lokare
Sr. Circuit Design Engineer
Analog Bits Inc.


About me
Pinless Clocking and Sensing
Modern day System on Chips are challenged by integration of arrays or processing
cores, SRAM’s and high-speed interconnects each needing is own optimized
clocking and sensing. Current solutions of integration of analog macros such as
PLL’s and PVT sensors requires dedicated analog power supply routing to the
macros causing congestion of routing in package traces cost addition with filter
components and form factor restrictions. Analog Bits’ newly patented package
pin-less technology for advanced FinFET nodes helps tackle these problems by
giving designers the freedom to integrate PVT Sensors and PLLs where they are
needed without concern for adding additional non-core voltage supply lines.
These IPs only need core supply voltage, so they are free from pad power bump
restrictions. This enables lower system power, less aging effects, lower pin
count, significant reduction in system costs and risk reduction with less things
to go wrong. Analog Bits will show silicon characterization of such macros in N5
and N4 processes and compare the performance to traditional analog power macros
demonstrating superior performance characteristics.   ...  
Graham Woods
Director of Applications Engineering
Agile Analog


About me
Analog lP Subsystems

Bhavana Chaurasia
Product Manager
Synopsys Inc


About me
Low Power Memory Solution for AIoT and Edge applications
Memory is ubiquitous in our smart everything world, the memory technology
landscape is changing quickly, with power becoming a key criterion.
High-performance computing, cloud, and AI applications need to conserve dynamic
power, while mobile, IoT, and edge applications are concerned about leakage
current. Synopsys sits in a unique position to support the growing memory
demand; we have broadest silicon-proven memory IP portfolio in the industry
across all major foundries and technology nodes. Our solution includes SRAMs,
ROM, MTP, OTP and eMRAMs. Our IPs are designed to meet higher compute density
with lower power.   ...  
David Eggleston
Sr. Business Development Manager
Silicon Storage Technology, Inc.


About me
eFlash IP for the AI & Chiplet Era

 
Break
11.40 am
Interconnect Solutions

Chairperson: David Jarmon, VeriSilicon, Inc.
Letizia Giuliano
Vice President Solution Engineering
Alphawave Semi


About me
Navigating Chiplet Design Today - Comprehensive toolsets for an open ecosystem
Today silicon design teams are being asked to do more and more. It’s not
surprising, given that our system-on-chip (SoC) devices are equipped with
greater power computing and connectivity. For many high-performance
applications—such as hyperscale data centers, AI, and autonomous
vehicles—monolithic SoCs are no longer enough. This drives demand for
multi-chiplet systems, in which multiple dies, or chiplets, are integrated into
a single System In Package (SIP). Multi-chiplets solutions are effective
solution, to be sure, but comes with greater challenge and requires the design
team to spend more time and resources to solve problems. For example, from
die-to-die connectivity IP selections, optimize power, area, and latency, and
select the right package technology for the most optimal total cost of ownership
for the complete SIP. How do you do it all efficiently and swiftly? How do you
reduce risk and time to market, and lower overall system power with increasing
throughput? How do you maintain a rapid pace in the creation of new product
variant This paper will present a toolset of solutions available to the next
generation of SOC to augment every step of the design cycle, like partitioning,
implementing, verifying, and signoff of more complex systems. We will explore
how to take an analysis-driven approach that considers architecture decisions
such as IP selections, hardware partitions, system-level power, and interconnect
dimensioning. We will provide methodology and solutions on several key areas can
enhance the design process: • Multi-chiplet system partitioning into dies to
optimize workload and interconnect traffic • Chip-to-chip communication
considerations to ensure optimal throughput and latency • Trade-offs between
interface power consumption, throughput, and die placement • Performance impact
of different fabrication and packaging technologies • Die-to-die protocols and
interfaces Lastly, this paper provides the list of cross-functional decision
metrics that ‘system-in-package’ design teams must consider when integrating
chiplets in an open-system, and also highlights the areas of improvement that
must be addressed in the current interface standard environment for chiplets.
Keywords—Chiplet, Standardizations, die-to-die, Interoperability, PCIe, CXL,
Form Factor,   ...  
Purna Mohanty
CEO
Marquee Semiconductor Inc.


About me
A proven silicon project management platform for complex SoCs and Chiplet based
sys-tems

Simon Butler
Methodics IPLM Founder & General Manager
Perforce Software


About me
IP Management Best Practices for Chiplet-Based SoCs

Manuel Mota
Sr. Product Marketing Manager
Synopsys, Inc.


About me
The Future of UCIe for Multi-Die Systems

1 pm
Lunch Break
1.45 pm
Network on Chip

Chairperson: Hugh Durdan, Independent Consultant
Parag Bhatt
VP of Engineering
Signature IP Corporation


About me
A Scalable, Configurable, Resilient Network-on-chip (NoC) for your complex SoC
and Chiplet-based Systems

Guillaume Boillet
Sr. Director of Product Management
Arteris IP


About me
Accelerating Schedules with Physical Awareness for Network-on-Chip (NoC) IP

 
Break
3 pm
Monitoring and Verification

Chairperson: Daniel Nenni, SemiWiki
Ash Patel
Director of Product Line Management, SLM, Synopsys
Synopsys


About me
Essential IP for the Enablement of Silicon Lifecycle Management
Silicon Lifecycle Management (SLM) is gaining momentum within the industry and
makes product development and deployment more deterministic by enabling greater
levels of observability into silicon health. Using embedded monitors as well as
existing test infrastructure allows real time, meaningful data to gathered at
every phase of the device lifecycle, this data is then transported off chip and
stored in a unified SLM database ready to be analysed. Based on this analysis,
insightful decisions can be made and the correct action taken. This foundation
of enriched in-chip observability, analytics, and integrated automation, enables
improved silicon health. In-chip environmental monitors provide real time data
on dynamic conditions like process variability, voltage supply and thermal
activity. Structural monitors enable the measurement of timing margins of real
functional paths. Functional monitors keep tab on critical functions of a SOC.
Alongside the embedded monitors, high speed access and test IP provides adaptive
high bandwidth testing over a functional interface, reducing test time and cost
with a lower pin count, enabling testing through entire silicon lifecycle. This
presentation will explain the importance of these essential IPs in enabling
effective management of the silicon lifecycle from In-Design, In-production,
In-Ramp and ultimately In-Field operation, as well as exploring some specific
use cases.   ...  
Lee Harrison
Director, Automotive IC Solutions
Siemens Digital Industries Software


About me
Next Generation Hardware based Cyber Security solution using advanced Embedded
Analytics monitoring technology
Modern IoT based systems such as connected and autonomous vehicles represent a
major cyber security challenge. As such, a clear need exists to monitor the
real-world operational behaviour of SoCs used in these secure electronics.
Existing software-based monitoring has numerous problems. By using the unique
hardware-based approach. With the deployment of Siemens Tessent Embedded
Analytics sentry and monitor IP, it is possible to deploy a security by design
approach that provides the benefits of being deeply embedded within the overall
system along with having an extremely low latency and response time to the
detection of dangerous cyber security attacks. In addition, the technology
brings visibility to key internal transactions of a system design that would not
otherwise be possible, the data collected from these internal transactions can
be used for offline system analysis as part of a wider SLM (Silicon Lifecycle
Management) Solution.   ...  
 
Break
4.00 pm
Interface IP

Chairperson: Kalar Rajendiran, SemiWiki
David Kulansky
Director
Alphawave Semi


About me
PAM4 PCIe -- Gen6 and beyond -- enabling the next gen of AI/ML

David Grugett
Sr. Manager of FAE
GOWIN Semiconductor


About me
The Future of USB Connectivity of FPGAs in Alternative Applications, Products,
and Markets
GOWIN offers multiple USB interface solutions including a USB v2.0 soft PHY and
the USB v2.0 Device Controller (SIE). The USB PHY and Device Controller allow
GOWIN FPGA designers to easily integrate USB connectivity to their end products
without the need for additional silicon ICs or devices. GOWIN’s USB solution is
useful for virtually every market segment including consumer, automotive,
industrial, and communications.   ...  


10.00 am
RISC-V Processor

Chairperson: Phil Dworsky, SiFive
Roger Espasa
CEO
Semidynamics Technology Services


About me
RISC-V OOO IP Core and Vector Unit
In this contribution we will describe Semidynamic's RISC-V IP comprising its
advanced family of out-of-order cores (code named Atrevido) and the companion
out-of-order vector unit, fully compliant to the RISC-V 1.0 specification. The
core and vector unit contain the Gazzillion(tm) misses technology, which make
them ideal for environments with high memory latency and/or high bandwidth
demands, such as CXL memory systems or HBM memory systems.   ...  
Larry Lapides
Vice President Sales
Imperas Software


About me
The Lost Art of Processor Verification

 
Break
11.00 am
Audio and video IP

Chairperson: Keith Hawkins, Ericsson
Casey Ng
Audio Marketing Director
Cadence Design Systems, Inc.


About me
TWS Applications with RISC-V and HiFi DSP
The RISC-V cpu and HiFi core combine to make an optimal solution. The RISC-V
architecture runs the Bluetooth stack and other operating software, while the
HiFi runs the audio related software.    With its ability to modularize and
customize for only the supported instructions, the RISC-V cpu helps optimize the
cost, while the HiFi core provides the essential audio processing such as the
LC3 codec and advanced features like Always On Keyword Spotting. Such
flexibility offer IoT and Bluetooth applications  power and cost-optimized
designs.In addition, the RISC-V PMP (physical memory protection) and support for
machine/supervisor/user mode makes the processor resilient to support supply
chain security and protect the software IPs.Several architecture examples will
be provided and discussions on their features, use cases and the design
resources to bring products to the market.   ...  
Hezi Saar
Senior Product Line Director
Synopsys, Inc.


About me
Advancement in Multimedia interfaces servicing Edge AI markets

Summer Yoon
Technical PR Manager
Chips&Media, Inc.


About me
Video IP Solution for Now and Beyond

Online Only
11.40 am
Ethernet IP and Networking

Chairperson: Keith Hawkins, Ericsson
Manmeet Walia
Product Manager Director
Synopsys, Inc.


About me
Driving the Future of High-Performance Computing through 224G Ethernet IP

Keith Hawkins
Head of ASIC COT
Ericsson


About me
5G drives exponential need in processing enabled by ASICs and IP ecosystem

12.20 pm
Lunch Break
1.00 pm
Artificial Intelligence SoC

Chairperson: Kyle Weng, OPENEDGES Technology, Inc.
Cheng Wang
Senior VP Software/Architecture, CTO & Co-Founder
Flex Logix Technologies, Inc.


About me
Fast, accurate and adaptable AI at low power, low cost
InferX is our silicon IP with Inference Compiler that performs very high
throughput AI and DSP at very low power/inference. We'll describe the building
blocks of our IP and how it scales and interfaces to the rest of the SoC. And
describe our Inference Compiler and run time APIs. Finally we'll give
performance and power benchmarks for FinFet nodes.   ...  
Mankit Lo
Chief Architect, NPU IP Development
VeriSilicon, Inc.


About me
AI-ISP: Adding Real-Time AI Functionality to Image Signal Processing with
Reduced Memory Footprint and Processing Latency

 
Break
2.00 pm
Automotive IP and space applications

Chairperson: Madhumita Sanyal, Synopsys, Inc.
Avi Zakai
Business Development of EBBM, Inc.
Digital Core Design


About me
New Horizontal Markets, Reap Benefits from Greater Avenues, using Controller
Area Networks

Jit Sur
Sales Engineer
CAST, Inc.


About me
FuSa IP Cores for Automotive

Chinh Le
CEO/CTO
LeWiz Communications, Inc.


About me
Space Applications - IP Core Challenges and Opportunities
Space: The final frontier! Full of challenges and opportunities for IP cores
commercial and open source. Space business is increasing rapidly both from the
government and private sectors. Space environment is very harsh and equipment
used for traveling, deploying to space require electronics that are high
reliability and radiation tolerant. Traveling to space is still a lengthy
process. Design and code will likely be obsolete before a launch or deployment
can take place. The majority of IP cores in commercial or open source do not
target for such environment. Yet, FPGA and ASIC devices developing for space
applications increase in size rapidly due to the industry’s move into nano-meter
silicon process. Large quantity of logic, memory and routing fabric are
available. Integrated SoCs require more and more cores – both digital and
analog. LeWiz and others developed a range of cores from RISC-V CPU to
peripherals that have been targeted for space applications. But more should be
done by the industry. This talk discusses the challenges and opportunities of
space applications for IP cores. It will also call on the open-source community
to contribute and advancing the state of the art in cores and associated tool
development for space applications.   ...  
 
Break
3.20 pm
Security Solutions

Chairperson: Sudhir Mallya, AlphaWave SEMI.
Matt Orzen
Director of Solution Architecture
Rambus, Inc.


About me
How to Secure Devices and Digital Assets with the Correct Root of Trust Solution

Wei Xu
Senior Staff FAE
Synopsys, Inc.


About me
Accelerating the Way Toward a Quantum-Safe Future

Alex Angelou
CEO of EBBM, Inc.
Digital Core Design


About me
Eliminate CyberSecurity Threats, from Product Designs, at the Silicon Level with
Post-Quantum Cryptographic Systems

Pim Tuyls
CEO
Intrinsic ID


About me
Securing System-in-Package with PUF Technology

Matti Tommiska

Xiphera Ltd


About me
Quantum-secure Signatures with Hardware-based Dilithium Core





 

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