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Home | Company | Blog | Test Strategies in the Era of Heterogeneous Integration

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September 5, 2023


TEST STRATEGIES IN THE ERA OF HETEROGENEOUS INTEGRATION

Moore’s Law, the observation that the number of transistors on an integrated
circuit doubles approximately every two years, is critical to advances in
computing technology. For decades, fabs have managed to achieve exponential
growth in digital capability and transistor density by making transistors
smaller and smaller but we’ve hit the physical limits of these processes. Today,
new process technologies and advanced packaging solutions, like chiplets, are
allowing the industry to continue the processing capabilities and digital
scaling of Moore’s Law. As early as 1965, even Gordon Moore noted: “It may be
more economical to build large systems out of smaller functions that are
individually packaged and interconnected.”

Although they have become more ubiquitous in recent years, chiplets face a
number of challenges in design, manufacturing, packaging and test. Because of
this, it is imperative to optimize the design-manufacture-test loop to continue
to reduce defect escape rates and cost of test while achieving the desired yield
targets and quality levels.

Optimizing the Total Cost of Quality is Critical

When dealing with more complex test processes such as known good die (KGD)
testing, final test, and system level test, strategies to optimize total cost of
quality are critical. Key points to consider include:

 * In the early stages of the design process, designers and test engineers need
   to use common tools to collaborate for chip verification and fault debugging
 * Moving some tests earlier in the overall process reduces defects before KGD
   integration
 * Reducing costs by deferring some tests to later in the manufacturing process
 * As manufacturing processes mature and stabilize, applying analytics to adjust
   the test processes before and during high volume manufacturing will optimize
   the overall cost of quality

Defect Escapes Lead to Exorbitant Scrap Costs

Compared with traditional monolithic devices, the design and manufacturing
process for chiplets is significantly different. The scrap costs associated with
manufacturing traditional monolithic semiconductor devices is basically linear,
including single chip cost, packaging, and assembly costs.

Manufacturing processes for 2.5D/3D designs differ significantly in terms of the
accumulation of scrap costs. Specifically, these costs increase geometrically
from fabrication to assembly driven by scrap costs for multiple dies, multi-chip
partial assemblies, and/or full 2.5D/3D packages.



Shift Left or Shift Right?

While 2.5D/3D packaging is an enabler of the next generation of Moore’s Law, the
economic viability of this approach requires reduced defect escape rates early
in the manufacturing process in an effort to reduce scrap costs. Shifting tests,
either left or right, in the test process is a strategy to achieve these goals
and minimize the overall manufacturing cost of 2.5D/3D components. Shift left is
the ability to increase test coverage earlier in the manufacturing process
(e.g., during wafer inspection and partial packaging) to maximize KGD, while
reducing future packaging costs. Additional tests can also be added to the
process to identify new failure types or failure modes.

However, the benefits of shift left need to be weighed. For example, increasing
test intensity early in the manufacturing process can positively impact known
good devices but it can also lead to an increase in test costs that is not
sufficiently offset by the optimizations, even after accounting for the
resulting reduction in scrap costs.

Shift right means increasing test coverage later in the manufacturing process,
expanding the ability to detect defects, and maintaining quality levels with the
goal of reducing costs with higher parallelism testing.

Typically, a test item with a higher yield on wafer or mission pattern tests, or
a high yield test that requires a longer scan test time is an ideal candidate
for shifting right. These tests can be moved to final or system level test, or
flexibly managed in between. The high level of parallelism achieved with system
level test for example delivers on the promise of economic improvements that can
only be achieved with multisite testing, further reducing costs while achieving
quality goals.

The goal of shifting tests to the left or right is to achieve the optimal
combination of quality and yield throughout the entire manufacturing process,
ultimately optimizing the overall cost of quality. Specific strategies include:

 * Minimizing scrap costs by reducing the defect escape rate in the wafer probe
   process
 * Realizing mass production testing in the most efficient way to reduce test
   costs
 * Implementing the closed-loop improvement of the entire manufacturing process
   through analytics, to increase the yield rate.

Teradyne’s FLEX Test solutions help you achieve this cost of quality with
flexible solutions that allow you to shift tests between insertions. Our strong
industry partnerships across EDA, fab/packaging and data analysis ensure this
process is seamless.



Data Analytics Drives Improved Decision-making

In the face of the choice to shift left or right, optimizing the test strategy
is a dynamic and continuous process, where analytics can play a key role in
informing these decisions. Teradyne’s Archimedes analytics solution can help
provide valuable data for adjusting test strategies throughout the chip
manufacturing process.



Teradyne Archimedes analytics solution integrates technologies like data
analytics, artificial intelligence and machine learning into your test solution,
enabling a secure stream of real-time data with near-zero test time impact that
can increase yield, improve quality, and reduce tester down time.

It’s an open development environment that supports both out of the box and
custom solutions to ensure insightful learnings can be realized for 2.5D/3D
packaged devices. Our tight integration with best-in-class
analytics providers ensures you can choose the solution that enables you to
achieve your goals for advanced devices.

Bridging the Gap from Design to Test

With chiplets, reducing defect escapes is not the only concern, yield must also
be taken into consideration. To achieve yield improvements, bridging the gap
from design to test is key to improving engineering efficiency. New workflows
require design, manufacturing and test engineering teams to work together
seamlessly to accelerate device development and generate learnings. Not only do
EDA and JTAG tools need to be enabled on ATE and SLT test systems, but it’s also
useful to have a common set of libraries and debug tools that allow design and
DFT engineers to seamlessly collaborate, sharing key insights, accelerating
silicon development, and reducing learning curves.

Teradyne’s PortBridge is a common toolset that bridges the gap between design
and test, and can be deployed at any stage of the manufacturing process to
identify, implement and verify opportunities for improving yield, including:

 * Debugging faults in system level test
 * Understanding faults in the final test insertion
 * Enhancing test coverage during wafer inspection to reduce defect escapes
 * Revealing inefficiencies in the production flow to improve device quality,
   reduce defects and increase yield



 

PortBridge works with Teradyne’s UltraFLEXplus and UltraFLEX testers and
provides:

 * Protocol Libraries for common protocols devices used today, and ones needed
   in the future. Usable all the way to production.
 * Remote Connect, built-in support to connect EDA tools and custom bench
   environments to the ATE remotely. Gets the right people looking at the
   problem, using the tools and environment they are familiar with.
 * Design File Support, which enables the use of standard design formats, like
   SVF, or custom formats, to eliminate conversion steps that waste time and
   lose valuable information
 * Host Debug Tools that deliver out-of-the-box, protocol-specific tools to
   expose the exact details needed while developing and debugging a test program
 * Production Enablement, the same protocol libraries can be used from debug to
   production to help with correlation, reduce overall effort and provide
   failure analysis with optimal test time.

With PortBridge, debug time is reduced from months to days with a platform- and
software-optimized solution.

While 2.5D/3D packaging technologies offer a path to continue the next
generation of Moore’s law, rapid identification of defects and quick
implementation of optimizations is the key to cost-effective, high-volume
manufacturing. A well-understood test process, where tests can be shifted left
or right to reduce the defect escape rate hence lowering scrap costs during the
manufacturing process is one strategy for minimizing the overall manufacturing
cost of these components. This flexibility, coupled with the integration of
capabilities in the design and test engineering domains, will facilitate the
rapid identification, debugging and elimination of faults while achieving the
best cost of quality. And while every stakeholder must do their part to increase
efficiency, collaboration across all of the key stakeholders and really the
entire industry is key to the success of achieving maximum operational
efficiency.

Contact us to learn more about Teradyne solutions that can help you achieve
optimal test processes.

Fisher Zhang is the general manager of the complex SOC business unit for
Teradyne’s Semiconductor Test Division in Asia, where he is focused on leading
edge solutions in computing, automotive and wireless. Fisher has been in
semiconductor industry for more than 17 years. Prior to joining Teradyne, he
held roles in applications engineering, sales and marketing at Advantest and
Cohu. Fisher holds a Bachelor of Science and Master of Science in circuits and
system and information engineering from Southeast University.


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