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SYSTEMC VERIFICATION



This page summarizes our activities around SystemC, a C++ class library
standardized by IEEE for modeling hardware/software systems. The result are
so-called Virtual Prototypes (VPs) which leverage Transaction Level Modeling
(TLM) to achieve orders of mangitue faster simulation performance compared to
RTL.

Besides our VP-based approaches, please also watch out for our activites around
our Constrained RAndom Verification Environment (CRAVE). For the full list on
our work around RISC-V, please visit: https://ics.jku.at/research/risc-v.

Your browser does not seem to support video streaming. You can download the
video manually here Snake demo on HiFive1 RISC-V VP vs real Hardware
Your browser does not seem to support video streaming. You can download the
video manually here GUI-VP Kit and networking: Loading a web page from the
Internet with a web-browser running on Linux and X.Org
Your browser does not seem to support video streaming. You can download the
video manually here GUI-VP Kit real-time interaction: Playing a Linux port of a
classic first-person 3D-game

New: Our virtual prototype RISCV-VP++ is available now at our ICS GitHub. RISCV
VP++ allows very fast Linux bootup, VNC, Vector Extension (RVV), 3D-game demos,
and more! Take a look at the GUI-VP Kit to get a quick and easy-to-use starting
point for experimenting with RISCV-VP++, Linux and interactive graphical
applications.


VP MODEL

 * A RISC-V “V” VP: Unlocking Vector Processing for Evaluation at the System
   Level (DATE 2024)
 * RISC-V VP++: Next generation open-source virtual prototype (OSDA 2024)
 * GUI-VP Kit: A RISC-V VP meets Linux graphics - enabling interactive graphical
   application development (GLSVLSI 2023)
 * Adaptive simulation with Virtual Prototypes in an open-source RISC-V
   evaluation platform (JSA 2021)
 * RISC-V based virtual prototype: An extensible and configurable platform for
   the system-level (JSA 2020)
 * Extensible and configurable RISC-V based virtual prototype (FDL 2018)


VP MODEL & CROSS-LEVEL VERIFICATION

 * Single instruction isolation for RISC-V vector test failures (ICCAD 2024)
 * Verifying SystemC TLM peripherals using modern C++ symbolic execution tools
   (DAC 2022)
 * An exploration platform for microcoded RISC-V cores leveraging the one
   instruction set computer principle (ISVLSI 2022)
 * Efficient cross-level processor verification using coverage-guided fuzzing
   (GLSVLSI 2022)
 * Efficient cross-level testing for processor verification: A RISC-V case-study
   (FDL 2020) (Received Best Paper Award)
 * Early verification of ISA extension specifications using deep reinforcement
   learning (GLSVLSI 2020)
 * Fast and accurate performance evaluation for RISC-V using virtual prototypes
   (DATE 2020)
 * Verifying instruction set simulators using coverage-guided fuzzing (DATE
   2019)


SOFTWARE/FIRMWARE VERIFICATION

 * Relation coverage: A new paradigm for hardware/software testing (ETS 2024)
 * Verifying embedded graphics libraries leveraging virtual prototypes and
   metamorphic testing (ASP-DAC 2024)
 * RVX - a tool for concolic testing of embedded binaries targeting RISC-V
   platforms (ATVA 2020)
 * Verification of embedded binaries using coverage-guided fuzzing with
   SystemC-based virtual prototypes (GLSVLSI 2020)
 * Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V
   Case Study (DAC 2019)


COMPLIANCE TESTING

 * Towards RISC-V CSR Compliance Testing (ESL 2021)
 * Closing the RISC-V compliance gap: Looking from the negative testing side
   (DAC 2020)
 * Towards specification and testing of RISC-V ISA compliance (DATE 2020)


SECURITY

 * Dynamic information flow tracking for embedded binaries using SystemC-based
   virtual prototypes (DAC 2020)
 * Detection of hardware trojans in SystemC HLS designs via coverage-guided
   fuzzing (DATE 2019)

JKU Institute for Complex Systems, Altenberger Straße 69, 4040 Linz, Austria,
Tel.: +43 732 2468 4561 – Imprint