digilent.frill.co Open in urlscan Pro
44.225.42.86  Public Scan

Form analysis
1 forms found in the DOM

Name: create-comment —

<form class="flex flex-col grow w-full relative z-1 rounded-md bg-surface-0 border border-surface-10" name="create-comment">
  <div class="flex relative flex-col grow" tabindex="-1">
    <div class="flex grow flex-col styles_size-md__Wn5Jv styles_padding-md__rEkqi m-px min-h-16 max-h-60 overflow-y-auto text-text"><span></span>
      <div class="flex flex-col space-y-2" role="textbox" aria-multiline="true" data-slate-editor="true" data-slate-node="value" contenteditable="true" zindex="-1"
        style="position: relative; outline: none; white-space: pre-wrap; overflow-wrap: break-word;">
        <div class="text-current" data-testid="editor-element-default" data-slate-node="element"><span data-slate-node="text"><span data-slate-leaf="true"><span data-slate-zero-width="n" data-slate-length="0"><br></span></span></span></div>
      </div>
      <div class="flex cursor-text grow min-h-0 outline-none" data-testid="editor-clickable-area" tabindex="-1"></div><span></span>
    </div>
  </div>
  <div class="flex w-full grow-0 shrink-0 items-end justify-between px-3 pt-2 pb-2.5">
    <div class="flex mr-2 min-w-0"></div>
    <div class="flex ml-auto shrink-0 items-center justify-between flex-row space-x-2">
      <div class="inline-flex relative">
        <div role="button" tabindex="0" type="button" class="button-reset flex w-7 h-7 items-center justify-center rounded-md hover:bg-surface-10 outline-none cursor-pointer">
          <div class="svg-icon inline-flex shrink-0 text-element-30 transition-colors" style="width: 0.875rem; height: 0.875rem;"><svg viewBox="0 0 14 14" xmlns="http://www.w3.org/2000/svg"
              class="block overflow-hidden pointer-events-none w-full h-full">
              <path
                d="m4.82811 10.2968 3.50817-5.01024c.5285-.75466.3451-1.7948-.4096-2.32322-.7547-.52842-1.79481-.34501-2.32322.40965l-3.98661 5.69351c-.85868 1.2263-.56065 2.9165.66567 3.7752 1.22632.8587 2.91655.5606 3.77523-.6657l3.86703-5.52265c1.233-1.76088.805-4.18787-.9559-5.42085-1.7608-1.23298-4.18783-.80503-5.4208.95584l-3.54808 5.06719"
                fill="none" stroke="currentColor" stroke-linecap="round" stroke-linejoin="round" transform="translate(2)"></path>
            </svg></div><input accept="image/*" hidden="" multiple="" name="file.create-comment" type="file">
        </div>
      </div><button type="submit" class="styles_btn___fK_8 styles_btn--xs__tsJpz styles_btn--brand__pQEEX"><span class="flex min-w-0 items-center opacity-100">Add comment</span></button>
    </div>
  </div>
</form>

Text Content

Ideas

Roadmap

Announcements

Search Ideas...

Log inSign up

 * 
   Ideas
 * 
   Roadmap
 * 
   Announcements

Statuses

 * 
   Under consideration
 * 
   Planned
 * 
   In Development
 * 
   Deployed

Topics

 * 
   New Feature
   3
 * 
   New Product
   5
 * 
   Improvement
   4
 * 
   Hardware
   3
 * 
   Software
   4
 * 
   FPGA
   3
 * 
   DAQ and Data Logging
   1
 * 
   Analog Discovery Series
   0
 * 
   Accessories
   1
 * 
   Waveforms
   0
 * 
   Software Defined Radio
   0
 * 
   Multisim Live
   0

Powered by frill.co



DIGILENT IDEA SPACE


Submit Idea

Have an idea for a product, feature, or improvement? This is the place where you
can share those ideas with Digilent’s product team as well as view and vote on
Ideas submitted by other Digilent users.



TrendingLatest IdeasMost votes


Filter
 1.  3
     
     
     PINNED
     WELCOME AND GUIDELINES
     
     Welcome to the Digilent Idea Space! If you have an idea for a product
     feature or improvement the floor is yours! Some guidelines: This space is
     purely for Ideas about new product features or improvements. Not support.
     The best place to find support is on our forums
     (https://forum.digilent.com/) and our reference library
     (https://digilent.com/reference/) Keep us lean There is a chance you aren't
     the first one to have your idea. Before submitting an idea, make sure to do
     a quick search. If you find an idea that is similar to your own, upvote it
     and leave a comment with any additional thoughts you think should be
     included in the idea. Add topic tags to your idea These help keep
     everything organized and easy to find. Some ideas span multiple topic tags.
     You can add multiple! If you don't have something nice to say....well you
     know.. Be kind :)
     
     Britt Espinosa19 Sep
     
     0

 2.  20
     
     
     
     A TEMPLATE/GENERATOR FOR AXI4-LITE IPS THAT TAKES REGISTER SPECIFICATIONS
     AS INPUT
     
     Xilinx's AXI IP template is known to have some bugs
     (https://zipcpu.com/blog/2021/05/22/vhdlaxil.html) and can be cumbersome
     for users who are brand new to using Zynq devices. A well-tested and
     protocol-compliant template that would allow users to create an IP directly
     from a description of the functionality they actually care about - the
     registers that connect to the logic they are trying to control - would
     significantly speed up this process. Similar open-source projects exist
     (https://github.com/rggen/rggen for example), however, the easiness of
     their integration into Vivado is questionable. Taking inspiration from
     rggen, an IP generator could be implemented in TCL which composes a
     AXI4-lite design including the desired functionality, described in a custom
     JSON format, which creates a fully packaged AXI IP including stub drivers
     to be brought up into Vitis/SDK through a BSP.
     
     Arthur B23 Aug
     #Improvement#FPGA
     Under consideration
     
     12

 3.  5
     
     
     
     ZYNQ SOM
     
     Many times I need some features of a development board that I can not find
     in the market boards. In this cases, SOM are very useful because I can
     develop my own board without the difficult of routing an FPGA or a DDR
     Memory. The idea is to create a board like CMOD but using a a Zynq.
     
     Pablo T29 Sep
     #New Product#FPGA#Hardware
     
     1

 4.  3
     
     
     
     GNU OCTAVE SUPPORT
     
     Create a plugin to support Digilent devices with GNU Octave.
     
     Britt Espinosa3 Oct
     #New Product#Software#Hardware
     
     1

 5.  1
     
     
     
     ZMOD 10G ETHERNET PHY
     
     Slow Pmod's won't handle the bandwidth needs for 10G, but Zmod (Syzygy)
     should.
     
     Bradford M15 Nov
     #New Product#Hardware#Accessories
     
     0

 6.  3
     
     
     
     ETHERNET DEVELOPMENT BOARD
     
     Since the trend is to more and more Ethernet based systems, a Board with a
     prety large SoC device would be interesting and at least 4 Ethernet boards
     would be great
     
     Sven M22 Sep
     #New Product
     
     0

 7.  3
     
     
     
     BRING BACK THE NETFPGA-1G-CML
     
     A board with 4 Gigabit Ethernet Ports, can be used for many applications
     for IIOT or Industry 4.0.
     
     Sven M22 Sep
     
     0

 8.  2
     
     
     
     SOFTWARE-CONTROLLED SAMPLE RATES ON THE ECLYPSE Z7
     
     Default sample rates in projects for the Eclypse Z7 usually test the limits
     of the Zmod hardware, using >40 MS/s sample rates. While this is useful for
     many users who want to look at small fast signals, other users who have
     lower-frequency signals of interest either need to work with buffers that
     are much larger than they actually wish to, or are potentially completely
     unable to capture said signal (in the case that buffers are too large fit
     in memory). Depending on the implementation, this may also allow the
     Eclypse to be used as a data logging device, capturing on the order of a
     point per second. A user posted on the Digiilent Forum wanting to vary the
     sample rate on the fly, in order to create equal-length buffers at
     different time scales:
     https://forum.digilent.com/topic/23725-memory-management-eclypse-z7/ This
     could be accomplished in a couple of different ways: Controlling clocking
     wizard IP via an AXI interface in order to reduce the sample rate -
     potentially requires modifications to front-end IP. Decimation/averaging of
     input streams in PL with ratios modifiable through AXI configuration IP.
     
     Arthur B2 Sep
     #New Feature#FPGA#DAQ and Data Logging
     
     0

 9.  2
     
     
     
     RUN PETALINUX AND STANDALONE OPERATING SYSTEMS ON DIFFERENT ZYNQ CPU CORES
     OF THE SAME BOARD AT THE SAME TIME
     
     A baremetal project could be run in one Zynq CPU which would provide a
     standard software interface to a Petalinux instance running on the other
     CPU. This would allow software development to be more easily split into two
     layers, one which can service PL hardware and hardware drivers in
     real-time, while the other could implement complex software and leverage
     premade libraries and drivers for things like data transport between the
     embedded device and the cloud or a host PC. Additionally, the separation of
     Petalinux development and baremetal project development would allow
     multiple developers to work in tandem, and allow the baremetal side to be
     tested on its own without the need for a complete solution. Such a project
     could target any number of boards, but a DMA-heavy system like a project
     for Eclypse or the Zybo Z7 would be ideal. The Petalinux layer could be
     used to export data (like captured video frames or signal acquisitions) to
     a host. Xilinx XAPP 1078 claims to implement such a system:
     https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841668/Multi-OS+Support+AMP+Hypervisor
     https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841653/XAPP1078+Latest+Information
     
     Arthur B24 Aug
     #Improvement#FPGA#New Feature
     
     0

 10. 1
     
     
     
     CMOD A7 WITH MORE I/O
     
     (Idea submitted to the Digilent forums, 07/27/2022) I like the CModA7 but
     wish it had a few more I/Os; I am always running out. A 64-pin dip module
     would be great.
     
     Britt Espinosa7 Oct
     #New Product#Hardware#Accessories
     
     1

 11. 1
     
     
     
     A DAQAMI TYPE SOFTWARE FOR LINUX
     
     MCC provides a (now free) Windows software app for monitoring and
     controlling MCC's USB and Ethernet products called DAQami. However there is
     no similar product for Linux users. alternatively, I don't know if there is
     a WaveForms app for Linux, but perhaps this would be a good place to start
     the Digilent + MCC product integration? that is assuming there in no
     interest in making a DAQami for Linux.
     
     Jeffrey G7 Sep
     #New Product#Software#Improvement
     
     0

 12. 1
     
     
     
     UPDATE THE DAQ HATS LIBRARY TO RUN ON THE LATEST RASPBERRY PI 64 BIT OS
     
     keeping up with the the Raspberry PI releases and features.
     
     Jeffrey G24 Aug
     #Improvement#Software#New Feature
     
     0

 13. 1
     
     
     
     DAQAMI ANNOTATIONS FOR SAVED CAPTURES
     
     (Idea submitted on the Digilent Forums, 7/13/2022) It would be really be
     useful when we save data captures to be able to add some notes about the
     test run that would accompany the files that are saved.
     
     Britt Espinosa22 Aug
     #Software#DAQ and Data Logging
     
     0

 * 
   Ideas
 * 
   Roadmap
 * 
   Announcements

Powered by frill.co

20



A TEMPLATE/GENERATOR FOR AXI4-LITE IPS THAT TAKES REGISTER SPECIFICATIONS AS
INPUT

Xilinx's AXI IP template is known to have some bugs
(https://zipcpu.com/blog/2021/05/22/vhdlaxil.html) and can be cumbersome for
users who are brand new to using Zynq devices. A well-tested and
protocol-compliant template that would allow users to create an IP directly from
a description of the functionality they actually care about - the registers that
connect to the logic they are trying to control - would significantly speed up
this process.

Similar open-source projects exist (https://github.com/rggen/rggen for example),
however, the easiness of their integration into Vivado is questionable.

Taking inspiration from rggen, an IP generator could be implemented in TCL which
composes a AXI4-lite design including the desired functionality, described in a
custom JSON format, which creates a fully packaged AXI IP including stub drivers
to be brought up into Vitis/SDK through a BSP.

Arthur B
23 Aug
A
K
Y

+17



#Improvement

#FPGA

Under consideration




Add comment
 * B
   
   Pinned
   
   Britt Espinosa
   Admin
   
   We currently have a beta open for this idea! Sign up for it here -->
   https://mautic.digilentinc.com/axi4-lite-ip-generator-beta-a
   
   
   2 days agoReply
   
   
 * J
   James A
   
   Very interesting to me.
   
   Would also like to see a tutorial wrapping a PMOD with an AXI4-Lite interface
   created by this tool.
   
   
   About 4 hours agoReply
   
   
 * K
   Kevin K
   
   Sounds like a great idea! Will users get access to the underlying VHDL code
   that is generated?
   
   
   A day agoReply
   
   
   Show reply
 * M
   Matteo V
   
   Is there going to be support for SystemRDL?
   
   
   A day agoReply
   
   
   Show reply
 * Y
   Yassen G
   
   Sounds promising. I would be glad to try it.
   
   
   A day agoReply
   
   
 * R
   Robert Douglas J
   
   I love this idea, having made axi4-light designs using Vivado before, that
   method is kind of cumbersome to create and update. If you have lots of
   registers or your create or edit these registers later, it is super painful
   to change. The idea of drivers for vitis also sounds amazing!
   
   
   A day agoReply
   
   
 * A
   Alpaslan S
   
   Hi
   
   Thank you so much. This is Good idea. i can trying to remotely
   
   
   A day agoReply
   
   
 * D
   Doru U
   
   Great for Creativity Laboratory ... work with studente and PhD candidates.
   
   
   A day agoReply
   
   
 * K
   KanZ K
   
   Wow! It's a very nice to me!! Thank you so much!!
   
   
   2 days agoReply
   
   
 * P
   Patrick D
   
   This is a good idea.
   
   
   2 days agoReply